Lines Matching defs:tdm_con
382 unsigned int tdm_con = 0;
400 tdm_con |= slave_mode << ETDM_IN1_CON0_REG_SLAVE_MODE_SFT;
401 tdm_con |= tdm_mode << ETDM_IN1_CON0_REG_FMT_SFT;
402 tdm_con |= (bit_width - 1) << ETDM_IN1_CON0_REG_BIT_LENGTH_SFT;
403 tdm_con |= (bit_width - 1) << ETDM_IN1_CON0_REG_WORD_LENGTH_SFT;
404 tdm_con |= (tdm_channels - 1) << ETDM_IN1_CON0_REG_CH_NUM_SFT;
406 tdm_con |= 0 << ETDM_IN1_CON0_REG_SYNC_MODE_SFT;
408 tdm_con |= 0 << ETDM_IN1_CON0_REG_RELATCH_1X_EN_SEL_DOMAIN_SFT;
409 regmap_update_bits(afe->regmap, ETDM_IN1_CON0, ETDM_IN_CON0_CTRL_MASK, tdm_con);
412 tdm_con = 0;
413 tdm_con |= 0 << ETDM_IN1_CON1_REG_LRCK_AUTO_MODE_SFT;
414 tdm_con |= 1 << ETDM_IN1_CON1_PINMUX_MCLK_CTRL_OE_SFT;
415 tdm_con |= (lrck_width - 1) << ETDM_IN1_CON1_REG_LRCK_WIDTH_SFT;
416 regmap_update_bits(afe->regmap, ETDM_IN1_CON1, ETDM_IN_CON1_CTRL_MASK, tdm_con);
419 tdm_con = 0;
420 tdm_con = ETDM_IN_CON3_FS(tran_rate);
421 regmap_update_bits(afe->regmap, ETDM_IN1_CON3, ETDM_IN_CON3_CTRL_MASK, tdm_con);
424 tdm_con = 0;
425 tdm_con = ETDM_IN_CON4_FS(tran_relatch_rate);
428 tdm_con |= ETDM_IN_CON4_CON0_SLAVE_LRCK_INV;
430 tdm_con |= ETDM_IN_CON4_CON0_SLAVE_BCK_INV;
433 tdm_con |= ETDM_IN_CON4_CON0_MASTER_LRCK_INV;
435 tdm_con |= ETDM_IN_CON4_CON0_MASTER_BCK_INV;
437 regmap_update_bits(afe->regmap, ETDM_IN1_CON4, ETDM_IN_CON4_CTRL_MASK, tdm_con);
440 tdm_con = 0;
442 tdm_con |= ETDM_IN_CON2_MULTI_IP_2CH_MODE;
443 tdm_con |= ETDM_IN_CON2_MULTI_IP_CH(channels);
445 regmap_update_bits(afe->regmap, ETDM_IN1_CON2, ETDM_IN_CON2_CTRL_MASK, tdm_con);
448 tdm_con = 0;
450 tdm_con |= 1 << ETDM_IN1_CON8_REG_ETDM_USE_AFIFO_SFT;
451 tdm_con |= 0 << ETDM_IN1_CON8_REG_AFIFO_CLOCK_DOMAIN_SEL_SFT;
452 tdm_con |= ETDM_IN_CON8_FS(tran_relatch_rate);
454 tdm_con |= 0 << ETDM_IN1_CON8_REG_ETDM_USE_AFIFO_SFT;
456 regmap_update_bits(afe->regmap, ETDM_IN1_CON8, ETDM_IN_CON8_CTRL_MASK, tdm_con);