Lines Matching refs:afe_priv
76 struct mt8186_afe_private *afe_priv = afe->platform_priv;
79 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
80 afe_priv->clk[clk_id]);
93 struct mt8186_afe_private *afe_priv = afe->platform_priv;
97 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
103 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
104 afe_priv->clk[CLK_TOP_APLL1_CK]);
113 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
119 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
120 afe_priv->clk[CLK_TOP_APLL1_D8]);
128 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
129 afe_priv->clk[CLK_CLK26M]);
136 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
138 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
139 afe_priv->clk[CLK_CLK26M]);
146 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
154 struct mt8186_afe_private *afe_priv = afe->platform_priv;
158 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
164 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
165 afe_priv->clk[CLK_TOP_APLL2_CK]);
174 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
180 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
181 afe_priv->clk[CLK_TOP_APLL2_D8]);
189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
190 afe_priv->clk[CLK_CLK26M]);
197 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
199 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
200 afe_priv->clk[CLK_CLK26M]);
207 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
215 struct mt8186_afe_private *afe_priv = afe->platform_priv;
220 ret = clk_prepare_enable(afe_priv->clk[i]);
233 struct mt8186_afe_private *afe_priv = afe->platform_priv;
237 clk_disable_unprepare(afe_priv->clk[i]);
242 struct mt8186_afe_private *afe_priv = afe->platform_priv;
245 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
252 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
259 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
265 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
266 afe_priv->clk[CLK_CLK26M]);
274 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
285 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
286 afe_priv->clk[CLK_TOP_APLL2_CK]);
294 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
304 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
309 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
311 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
313 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
315 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
322 struct mt8186_afe_private *afe_priv = afe->platform_priv;
324 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
326 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
327 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
328 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
329 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
334 struct mt8186_afe_private *afe_priv = afe->platform_priv;
338 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
348 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
355 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
361 struct mt8186_afe_private *afe_priv = afe->platform_priv;
365 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
376 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
383 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
389 struct mt8186_afe_private *afe_priv = afe->platform_priv;
395 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
402 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
418 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
420 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
427 struct mt8186_afe_private *afe_priv = afe->platform_priv;
434 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
435 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
442 struct mt8186_afe_private *afe_priv = afe->platform_priv;
448 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
455 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
471 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
473 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
480 struct mt8186_afe_private *afe_priv = afe->platform_priv;
487 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
488 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
542 struct mt8186_afe_private *afe_priv = afe->platform_priv;
552 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
558 ret = clk_set_parent(afe_priv->clk[m_sel_id],
559 afe_priv->clk[apll_clk_id]);
569 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
575 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
587 struct mt8186_afe_private *afe_priv = afe->platform_priv;
591 clk_disable_unprepare(afe_priv->clk[div_clk_id]);
593 clk_disable_unprepare(afe_priv->clk[m_sel_id]);
598 struct mt8186_afe_private *afe_priv = afe->platform_priv;
604 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
606 if (!afe_priv->clk)
610 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
611 if (IS_ERR(afe_priv->clk[i])) {
614 aud_clks[i], PTR_ERR(afe_priv->clk[i]));
615 afe_priv->clk[i] = NULL;
619 afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node,
621 if (IS_ERR(afe_priv->apmixedsys)) {
623 __func__, PTR_ERR(afe_priv->apmixedsys));
624 return PTR_ERR(afe_priv->apmixedsys);
627 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node,
629 if (IS_ERR(afe_priv->topckgen)) {
631 __func__, PTR_ERR(afe_priv->topckgen));
632 return PTR_ERR(afe_priv->topckgen);
635 afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node,
637 if (IS_ERR(afe_priv->infracfg)) {
639 __func__, PTR_ERR(afe_priv->infracfg));
640 return PTR_ERR(afe_priv->infracfg);