Lines Matching defs:cdev
29 struct dma_chan *catpt_dma_request_config_chan(struct catpt_dev *cdev)
39 chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev);
41 dev_err(cdev->dev, "request channel failed\n");
54 dev_err(cdev->dev, "slave config failed: %d\n", ret);
62 static int catpt_dma_memcpy(struct catpt_dev *cdev, struct dma_chan *chan,
73 dev_err(cdev->dev, "prep dma memcpy failed\n");
78 catpt_updatel_shim(cdev, HMDC,
84 dev_err(cdev->dev, "submit tx failed: %d\n", ret);
93 catpt_updatel_shim(cdev, HMDC,
99 int catpt_dma_memcpy_todsp(struct catpt_dev *cdev, struct dma_chan *chan,
103 return catpt_dma_memcpy(cdev, chan, dst_addr | CATPT_DMA_DSP_ADDR_MASK,
107 int catpt_dma_memcpy_fromdsp(struct catpt_dev *cdev, struct dma_chan *chan,
111 return catpt_dma_memcpy(cdev, chan, dst_addr,
115 int catpt_dmac_probe(struct catpt_dev *cdev)
120 dmac = devm_kzalloc(cdev->dev, sizeof(*dmac), GFP_KERNEL);
124 dmac->regs = cdev->lpe_ba + cdev->spec->host_dma_offset[CATPT_DMA_DEVID];
125 dmac->dev = cdev->dev;
126 dmac->irq = cdev->irq;
128 ret = dma_coerce_mask_and_coherent(cdev->dev, DMA_BIT_MASK(31));
139 cdev->dmac = dmac;
143 void catpt_dmac_remove(struct catpt_dev *cdev)
151 dw_dma_remove(cdev->dmac);
154 static void catpt_dsp_set_srampge(struct catpt_dev *cdev, struct resource *sram,
161 old = catpt_readl_pci(cdev, VDRTCTL0) & mask;
162 dev_dbg(cdev->dev, "SRAMPGE [0x%08lx] 0x%08lx -> 0x%08lx",
168 catpt_updatel_pci(cdev, VDRTCTL0, mask, new);
181 dev_dbg(cdev->dev, "sanitize block %ld: off 0x%08x\n",
183 memcpy_fromio(buf, cdev->lpe_ba + off, sizeof(buf));
189 void catpt_dsp_update_srampge(struct catpt_dev *cdev, struct resource *sram,
208 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0);
210 catpt_dsp_set_srampge(cdev, sram, mask, new);
213 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE,
217 int catpt_dsp_stall(struct catpt_dev *cdev, bool stall)
222 catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val);
224 return catpt_readl_poll_shim(cdev, CS1,
229 static int catpt_dsp_reset(struct catpt_dev *cdev, bool reset)
234 catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val);
236 return catpt_readl_poll_shim(cdev, CS1,
241 void lpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable)
246 catpt_updatel_pci(cdev, VDRTCTL0, LPT_VDRTCTL0_APLLSE, val);
249 void wpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable)
254 catpt_updatel_pci(cdev, VDRTCTL2, WPT_VDRTCTL2_APLLSE, val);
257 static int catpt_dsp_select_lpclock(struct catpt_dev *cdev, bool lp, bool waiti)
262 mutex_lock(&cdev->clk_mutex);
265 reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS;
266 dev_dbg(cdev->dev, "LPCS [0x%08lx] 0x%08x -> 0x%08x",
270 mutex_unlock(&cdev->clk_mutex);
276 ret = catpt_readl_poll_shim(cdev, ISD,
280 dev_warn(cdev->dev, "await WAITI timeout\n");
283 mutex_unlock(&cdev->clk_mutex);
289 ret = catpt_readl_poll_shim(cdev, CLKCTL,
293 dev_warn(cdev->dev, "clock change still in progress\n");
298 catpt_updatel_shim(cdev, CS1, mask, val);
300 ret = catpt_readl_poll_shim(cdev, CLKCTL,
304 dev_warn(cdev->dev, "clock change still in progress\n");
307 cdev->spec->pll_shutdown(cdev, lp);
309 mutex_unlock(&cdev->clk_mutex);
313 int catpt_dsp_update_lpclock(struct catpt_dev *cdev)
317 list_for_each_entry(stream, &cdev->stream_list, node)
319 return catpt_dsp_select_lpclock(cdev, false, true);
321 return catpt_dsp_select_lpclock(cdev, true, true);
325 static void catpt_dsp_set_regs_defaults(struct catpt_dev *cdev)
329 catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT);
330 catpt_writel_shim(cdev, ISC, CATPT_ISC_DEFAULT);
331 catpt_writel_shim(cdev, ISD, CATPT_ISD_DEFAULT);
332 catpt_writel_shim(cdev, IMC, CATPT_IMC_DEFAULT);
333 catpt_writel_shim(cdev, IMD, CATPT_IMD_DEFAULT);
334 catpt_writel_shim(cdev, IPCC, CATPT_IPCC_DEFAULT);
335 catpt_writel_shim(cdev, IPCD, CATPT_IPCD_DEFAULT);
336 catpt_writel_shim(cdev, CLKCTL, CATPT_CLKCTL_DEFAULT);
337 catpt_writel_shim(cdev, CS2, CATPT_CS2_DEFAULT);
338 catpt_writel_shim(cdev, LTRC, CATPT_LTRC_DEFAULT);
339 catpt_writel_shim(cdev, HMDC, CATPT_HMDC_DEFAULT);
342 catpt_writel_ssp(cdev, i, SSCR0, CATPT_SSC0_DEFAULT);
343 catpt_writel_ssp(cdev, i, SSCR1, CATPT_SSC1_DEFAULT);
344 catpt_writel_ssp(cdev, i, SSSR, CATPT_SSS_DEFAULT);
345 catpt_writel_ssp(cdev, i, SSITR, CATPT_SSIT_DEFAULT);
346 catpt_writel_ssp(cdev, i, SSDR, CATPT_SSD_DEFAULT);
347 catpt_writel_ssp(cdev, i, SSTO, CATPT_SSTO_DEFAULT);
348 catpt_writel_ssp(cdev, i, SSPSP, CATPT_SSPSP_DEFAULT);
349 catpt_writel_ssp(cdev, i, SSTSA, CATPT_SSTSA_DEFAULT);
350 catpt_writel_ssp(cdev, i, SSRSA, CATPT_SSRSA_DEFAULT);
351 catpt_writel_ssp(cdev, i, SSTSS, CATPT_SSTSS_DEFAULT);
352 catpt_writel_ssp(cdev, i, SSCR2, CATPT_SSCR2_DEFAULT);
353 catpt_writel_ssp(cdev, i, SSPSP2, CATPT_SSPSP2_DEFAULT);
357 int catpt_dsp_power_down(struct catpt_dev *cdev)
362 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0);
364 catpt_dsp_reset(cdev, true);
366 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1),
368 catpt_dsp_select_lpclock(cdev, true, false);
370 catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, 0);
372 catpt_dsp_set_regs_defaults(cdev);
377 catpt_updatel_pci(cdev, VDRTCTL2, mask, val);
379 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DTCGE,
383 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask,
384 cdev->spec->dram_mask);
385 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask,
386 cdev->spec->iram_mask);
387 mask = cdev->spec->d3srampgd_bit | cdev->spec->d3pgd_bit;
388 catpt_updatel_pci(cdev, VDRTCTL0, mask, cdev->spec->d3pgd_bit);
390 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot);
395 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE,
402 int catpt_dsp_power_up(struct catpt_dev *cdev)
407 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0);
412 catpt_updatel_pci(cdev, VDRTCTL2, mask, val);
414 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0);
417 mask = cdev->spec->d3srampgd_bit | cdev->spec->d3pgd_bit;
418 catpt_updatel_pci(cdev, VDRTCTL0, mask, mask);
419 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 0);
420 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 0);
422 catpt_dsp_set_regs_defaults(cdev);
425 catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, CATPT_CLKCTL_SMOS);
426 catpt_dsp_select_lpclock(cdev, false, false);
428 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1),
430 catpt_dsp_reset(cdev, false);
433 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE,
437 catpt_updatel_shim(cdev, IMC, CATPT_IMC_IPCDB | CATPT_IMC_IPCCD, 0);
456 int catpt_coredump(struct catpt_dev *cdev)
468 dump_size = resource_size(&cdev->dram);
469 dump_size += resource_size(&cdev->iram);
482 hdr->core_id = cdev->spec->core_id;
487 info = cdev->ipc.config.fw_info;
503 hdr->core_id = cdev->spec->core_id;
505 hdr->size = resource_size(&cdev->iram);
508 memcpy_fromio(pos, cdev->lpe_ba + cdev->iram.start, hdr->size);
513 hdr->core_id = cdev->spec->core_id;
515 hdr->size = resource_size(&cdev->dram);
518 memcpy_fromio(pos, cdev->lpe_ba + cdev->dram.start, hdr->size);
523 hdr->core_id = cdev->spec->core_id;
528 memcpy_fromio(pos, catpt_shim_addr(cdev), CATPT_SHIM_REGS_SIZE);
532 memcpy_fromio(pos, catpt_ssp_addr(cdev, i),
537 memcpy_fromio(pos, catpt_dma_addr(cdev, i),
542 dev_coredumpv(cdev->dev, dump, dump_size, GFP_KERNEL);