Lines Matching refs:i2s
32 #include "hi6210-i2s.h"
81 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
83 writel(val, i2s->base + reg);
86 static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
88 return readl(i2s->base + reg);
94 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
99 regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
101 regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
103 for (n = 0; n < i2s->clocks; n++) {
104 ret = clk_prepare_enable(i2s->clk[n]);
109 ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
111 dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
117 regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
120 regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
123 regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
124 regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
126 /* not interested in i2s irqs */
127 val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
129 hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
133 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
135 hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
137 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
139 hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
142 val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
146 hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
148 val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
149 /* mux 11/12 = APB not i2s */
158 hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
160 val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
162 hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
168 clk_disable_unprepare(i2s->clk[n]);
175 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
178 for (n = 0; n < i2s->clocks; n++)
179 clk_disable_unprepare(i2s->clk[n]);
181 regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
186 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
189 spin_lock(&i2s->lock);
192 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
194 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
197 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
199 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
201 spin_unlock(&i2s->lock);
206 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
209 spin_lock(&i2s->lock);
211 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
213 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
215 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
217 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
219 spin_unlock(&i2s->lock);
224 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
247 i2s->format = fmt;
248 i2s->master = (i2s->format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
258 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
315 i2s->bits = 32;
319 i2s->bits = 16;
323 i2s->rate = params_rate(params);
324 i2s->channels = params_channels(params);
325 i2s->channel_length = i2s->channels * i2s->bits;
327 val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
340 hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
343 val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
350 hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
353 val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
362 hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
365 val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
368 hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
370 val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
375 hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
378 switch (i2s->format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
380 i2s->master = false;
381 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
383 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
386 i2s->master = true;
387 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
389 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
392 WARN_ONCE(1, "Invalid i2s->fmt CLOCK_PROVIDER_MASK. This shouldn't happen\n");
396 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
407 WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
411 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
415 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
418 val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
421 hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
426 dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
428 dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
430 switch (i2s->channels) {
432 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
434 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
437 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
439 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
444 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
452 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
455 if (!i2s->master)
459 val = hi6210_read_reg(i2s, HII2S_FS_CFG);
470 hi6210_write_reg(i2s, HII2S_FS_CFG, val);
503 struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
506 &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
507 &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
541 .name = "hi6210_i2s-i2s",
549 struct hi6210_i2s *i2s;
553 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
554 if (!i2s)
557 i2s->dev = dev;
558 spin_lock_init(&i2s->lock);
560 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
561 if (IS_ERR(i2s->base))
562 return PTR_ERR(i2s->base);
564 i2s->base_phys = (phys_addr_t)res->start;
565 i2s->dai = hi6210_i2s_dai_init;
567 dev_set_drvdata(dev, i2s);
569 i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
571 if (IS_ERR(i2s->sysctrl))
572 return PTR_ERR(i2s->sysctrl);
574 i2s->clk[CLK_DACODEC] = devm_clk_get(dev, "dacodec");
575 if (IS_ERR(i2s->clk[CLK_DACODEC]))
576 return PTR_ERR(i2s->clk[CLK_DACODEC]);
577 i2s->clocks++;
579 i2s->clk[CLK_I2S_BASE] = devm_clk_get(dev, "i2s-base");
580 if (IS_ERR(i2s->clk[CLK_I2S_BASE]))
581 return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
582 i2s->clocks++;
589 &i2s->dai, 1);
594 { .compatible = "hisilicon,hi6210-i2s" },