Lines Matching refs:xcvr
98 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
102 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]);
111 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
113 ucontrol->value.enumerated.item[0] = xcvr->arc_mode;
143 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
145 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
154 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
156 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE);
201 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
207 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]);
210 (xcvr->mode == FSL_XCVR_MODE_ARC));
212 (xcvr->mode == FSL_XCVR_MODE_EARC));
216 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0);
224 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
226 ucontrol->value.enumerated.item[0] = xcvr->mode;
239 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
241 struct device *dev = &xcvr->pdev->dev;
248 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
249 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
250 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
251 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
253 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
262 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
264 struct device *dev = &xcvr->pdev->dev;
268 if (xcvr->soc_data->spdif_only)
284 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
292 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
296 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
298 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
300 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
302 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
306 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
311 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
314 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
316 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
318 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
321 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
325 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
328 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
332 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
334 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
338 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
341 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
343 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
346 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
349 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1);
358 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
360 struct device *dev = &xcvr->pdev->dev;
363 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
364 clk_disable_unprepare(xcvr->phy_clk);
365 ret = clk_set_rate(xcvr->phy_clk, freq);
370 ret = clk_prepare_enable(xcvr->phy_clk);
376 if (xcvr->soc_data->spdif_only)
379 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
386 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
388 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
392 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
396 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
410 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
417 switch (xcvr->mode) {
419 if (xcvr->soc_data->spdif_only && tx) {
420 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
431 ret = fsl_xcvr_en_aud_pll(xcvr, fout);
438 ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
456 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
466 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
477 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
486 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR,
503 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
513 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
545 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
549 if (xcvr->streams & BIT(substream->stream)) {
558 if (xcvr->soc_data->use_edma)
561 tx ? xcvr->dma_prms_tx.maxburst :
562 xcvr->dma_prms_rx.maxburst);
564 switch (xcvr->mode) {
578 xcvr->streams |= BIT(substream->stream);
580 if (!xcvr->soc_data->spdif_only) {
597 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
602 xcvr->streams &= ~BIT(substream->stream);
605 if (!xcvr->streams) {
606 if (!xcvr->soc_data->spdif_only) {
612 (xcvr->mode == FSL_XCVR_MODE_ARC));
614 (xcvr->mode == FSL_XCVR_MODE_EARC));
617 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
625 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
629 if (xcvr->mode == FSL_XCVR_MODE_EARC) {
635 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
645 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
654 switch (xcvr->mode) {
657 ret = regmap_write(xcvr->regmap,
666 ret = regmap_write(xcvr->regmap,
678 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
686 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
699 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
708 switch (xcvr->mode) {
710 ret = regmap_write(xcvr->regmap,
717 if (xcvr->soc_data->spdif_only)
723 ret = regmap_write(xcvr->regmap,
742 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
744 struct device *dev = &xcvr->pdev->dev;
749 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev);
765 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
779 memcpy_toio(xcvr->ram_addr, fw->data + off, out);
784 memset_io(xcvr->ram_addr + out, 0, size - out);
788 memset_io(xcvr->ram_addr, 0, size);
808 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
815 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
842 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
844 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24);
853 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
855 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24);
864 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
866 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24);
913 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
915 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
917 if (xcvr->soc_data->spdif_only)
918 xcvr->mode = FSL_XCVR_MODE_SPDIF;
962 .name = "fsl-xcvr-dai",
1018 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1020 if (xcvr->soc_data->spdif_only)
1091 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1093 if (xcvr->soc_data->spdif_only)
1161 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
1162 struct device *dev = &xcvr->pdev->dev;
1163 struct regmap *regmap = xcvr->regmap;
1172 if (!xcvr->soc_data->spdif_only) {
1174 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1179 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
1180 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
1183 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
1184 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
1190 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
1191 sizeof(xcvr->rx_iec958.status));
1193 val = *(u32 *)(xcvr->rx_iec958.status + i*4);
1194 *(u32 *)(xcvr->rx_iec958.status + i*4) =
1236 .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
1245 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1246 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
1254 struct fsl_xcvr *xcvr;
1259 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL);
1260 if (!xcvr)
1263 xcvr->pdev = pdev;
1264 xcvr->soc_data = of_device_get_match_data(&pdev->dev);
1266 xcvr->ipg_clk = devm_clk_get(dev, "ipg");
1267 if (IS_ERR(xcvr->ipg_clk)) {
1269 return PTR_ERR(xcvr->ipg_clk);
1272 xcvr->phy_clk = devm_clk_get(dev, "phy");
1273 if (IS_ERR(xcvr->phy_clk)) {
1275 return PTR_ERR(xcvr->phy_clk);
1278 xcvr->spba_clk = devm_clk_get(dev, "spba");
1279 if (IS_ERR(xcvr->spba_clk)) {
1281 return PTR_ERR(xcvr->spba_clk);
1284 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg");
1285 if (IS_ERR(xcvr->pll_ipg_clk)) {
1287 return PTR_ERR(xcvr->pll_ipg_clk);
1290 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
1291 if (IS_ERR(xcvr->ram_addr))
1292 return PTR_ERR(xcvr->ram_addr);
1298 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs,
1300 if (IS_ERR(xcvr->regmap)) {
1302 PTR_ERR(xcvr->regmap));
1303 return PTR_ERR(xcvr->regmap);
1306 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
1307 if (IS_ERR(xcvr->reset)) {
1309 return PTR_ERR(xcvr->reset);
1317 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
1329 xcvr->dma_prms_rx.chan_name = "rx";
1330 xcvr->dma_prms_tx.chan_name = "tx";
1331 xcvr->dma_prms_rx.addr = rx_res->start;
1332 xcvr->dma_prms_tx.addr = tx_res->start;
1333 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX;
1334 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX;
1336 platform_set_drvdata(pdev, xcvr);
1338 regcache_cache_only(xcvr->regmap, true);
1369 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1377 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
1382 if (!xcvr->soc_data->spdif_only) {
1384 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1391 regcache_cache_only(xcvr->regmap, true);
1393 clk_disable_unprepare(xcvr->spba_clk);
1394 clk_disable_unprepare(xcvr->phy_clk);
1395 clk_disable_unprepare(xcvr->pll_ipg_clk);
1396 clk_disable_unprepare(xcvr->ipg_clk);
1403 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1406 ret = reset_control_assert(xcvr->reset);
1412 ret = clk_prepare_enable(xcvr->ipg_clk);
1418 ret = clk_prepare_enable(xcvr->pll_ipg_clk);
1424 ret = clk_prepare_enable(xcvr->phy_clk);
1430 ret = clk_prepare_enable(xcvr->spba_clk);
1436 regcache_cache_only(xcvr->regmap, false);
1437 regcache_mark_dirty(xcvr->regmap);
1438 ret = regcache_sync(xcvr->regmap);
1445 if (xcvr->soc_data->spdif_only)
1448 ret = reset_control_deassert(xcvr->reset);
1454 ret = fsl_xcvr_load_firmware(xcvr);
1461 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1474 clk_disable_unprepare(xcvr->spba_clk);
1476 clk_disable_unprepare(xcvr->phy_clk);
1478 clk_disable_unprepare(xcvr->pll_ipg_clk);
1480 clk_disable_unprepare(xcvr->ipg_clk);
1496 .name = "fsl,imx8mp-audio-xcvr",