Lines Matching refs:ret
243 int ret;
253 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
256 if (ret)
259 return ret;
266 int ret;
284 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
286 if (ret < 0) {
287 dev_err(dev, "Error while setting IER0: %d\n", ret);
288 return ret;
361 int ret;
365 ret = clk_set_rate(xcvr->phy_clk, freq);
366 if (ret < 0) {
367 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
368 return ret;
370 ret = clk_prepare_enable(xcvr->phy_clk);
371 if (ret) {
372 dev_err(dev, "failed to start PHY clock: %d\n", ret);
373 return ret;
379 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
381 if (ret < 0) {
382 dev_err(dev, "Error while setting IER0: %d\n", ret);
383 return ret;
415 int ret = 0;
420 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
423 if (ret < 0) {
424 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret);
425 return ret;
431 ret = fsl_xcvr_en_aud_pll(xcvr, fout);
432 if (ret < 0) {
434 fout, ret);
435 return ret;
438 ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
440 if (ret < 0) {
441 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret);
442 return ret;
456 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
461 if (ret < 0) {
462 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
463 return ret;
466 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
467 if (ret < 0) {
469 FSL_XCVR_SPDIF_RX_FREQ, ret);
470 return ret;
477 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
480 if (ret < 0) {
481 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
482 return ret;
486 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR,
489 if (ret < 0) {
490 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret);
491 return ret;
503 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
505 if (ret < 0) {
506 dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
507 return ret;
513 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
514 if (ret < 0) {
515 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
516 return ret;
527 int ret;
529 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
531 if (ret < 0)
532 return ret;
534 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE,
536 if (ret < 0)
537 return ret;
547 int ret = 0;
567 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
571 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr,
575 if (ret < 0)
576 return ret;
600 int ret;
617 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
619 if (ret < 0) {
620 dev_err(dai->dev, "Failed to set IER0: %d\n", ret);
635 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
636 if (ret < 0) {
637 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
647 int ret;
657 ret = regmap_write(xcvr->regmap,
660 if (ret < 0) {
661 dev_err(dai->dev, "err updating isr %d\n", ret);
662 return ret;
666 ret = regmap_write(xcvr->regmap,
669 if (ret < 0) {
670 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
671 return ret;
678 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
680 if (ret < 0) {
681 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
682 return ret;
686 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
689 if (ret < 0) {
690 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
691 return ret;
699 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
702 if (ret < 0) {
703 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
704 return ret;
710 ret = regmap_write(xcvr->regmap,
713 if (ret < 0) {
714 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
715 return ret;
723 ret = regmap_write(xcvr->regmap,
726 if (ret < 0) {
728 "Err updating ISR %d\n", ret);
729 return ret;
746 int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET;
749 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev);
750 if (ret) {
752 return ret;
765 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
768 if (ret < 0) {
770 page, ret);
794 if (ret < 0)
795 return ret;
808 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
809 if (ret < 0) {
810 dev_err(dev, "Failed to set watermarks: %d\n", ret);
811 return ret;
1257 int ret, irq;
1317 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
1318 if (ret) {
1319 dev_err(dev, "failed to claim IRQ0: %i\n", ret);
1320 return ret;
1344 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1345 if (ret) {
1348 return ret;
1351 ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp,
1353 if (ret) {
1359 return ret;
1370 int ret;
1377 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
1379 if (ret < 0)
1380 dev_err(dev, "Failed to clear IER0: %d\n", ret);
1384 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1387 if (ret < 0)
1388 dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
1404 int ret;
1406 ret = reset_control_assert(xcvr->reset);
1407 if (ret < 0) {
1408 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret);
1409 return ret;
1412 ret = clk_prepare_enable(xcvr->ipg_clk);
1413 if (ret) {
1415 return ret;
1418 ret = clk_prepare_enable(xcvr->pll_ipg_clk);
1419 if (ret) {
1424 ret = clk_prepare_enable(xcvr->phy_clk);
1425 if (ret) {
1426 dev_err(dev, "failed to start PHY clock: %d\n", ret);
1430 ret = clk_prepare_enable(xcvr->spba_clk);
1431 if (ret) {
1438 ret = regcache_sync(xcvr->regmap);
1440 if (ret) {
1448 ret = reset_control_deassert(xcvr->reset);
1449 if (ret) {
1454 ret = fsl_xcvr_load_firmware(xcvr);
1455 if (ret) {
1461 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1463 if (ret < 0) {
1464 dev_err(dev, "M0+ core release failed: %d\n", ret);
1482 return ret;