Lines Matching refs:ssi
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
344 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
345 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
346 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
347 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
352 static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
354 return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
358 static bool fsl_ssi_is_i2s_clock_provider(struct fsl_ssi *ssi)
360 return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
364 static bool fsl_ssi_is_i2s_bc_fp(struct fsl_ssi *ssi)
366 return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
377 struct fsl_ssi *ssi = dev_id;
378 struct regmap *regs = ssi->regs;
383 sisr2 = sisr & ssi->soc->sisr_write_mask;
388 fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
396 * @ssi: SSI context
404 static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
406 struct fsl_ssi_regvals *vals = ssi->regvals;
411 regmap_update_bits(ssi->regs, REG_SSI_SOR,
419 if (ssi->soc->offline_config && ssi->streams)
422 if (ssi->soc->offline_config) {
438 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
439 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
440 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
449 if (ssi->use_dma && tx) {
454 regmap_update_bits(ssi->regs, REG_SSI_SCR,
459 regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
466 dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
469 regmap_update_bits(ssi->regs, REG_SSI_SCR,
473 ssi->streams |= BIT(dir);
499 * @ssi: SSI context
507 static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
516 aactive = ssi->streams & BIT(adir);
518 vals = &ssi->regvals[dir];
521 avals = &ssi->regvals[adir];
530 regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
533 ssi->streams &= ~BIT(dir);
539 if (ssi->soc->offline_config && aactive)
542 if (ssi->soc->offline_config) {
558 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
559 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
560 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
564 regmap_update_bits(ssi->regs, REG_SSI_SOR,
568 static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
570 struct regmap *regs = ssi->regs;
573 if (!ssi->soc->imx21regs) {
584 * @ssi: SSI context
586 static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
588 struct fsl_ssi_regvals *vals = ssi->regvals;
598 if (fsl_ssi_is_ac97(ssi))
601 if (ssi->use_dual_fifo) {
606 if (ssi->use_dma) {
615 static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
617 struct regmap *regs = ssi->regs;
638 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
641 ret = clk_prepare_enable(ssi->clk);
651 if (ssi->use_dual_fifo || ssi->use_dyna_fifo)
662 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
664 clk_disable_unprepare(ssi->clk);
684 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
685 struct regmap *regs = ssi->regs;
697 if (ssi->slots)
698 slots = ssi->slots;
699 if (ssi->slot_width)
700 slot_width = ssi->slot_width;
704 (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
711 if (IS_ERR(ssi->baudclk))
718 if (freq * 5 > clk_get_rate(ssi->clk)) {
723 baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
735 clkrate = clk_get_rate(ssi->baudclk);
737 clkrate = clk_round_rate(ssi->baudclk, tmprate);
776 tx2 = tx || ssi->synchronous;
780 ret = clk_set_rate(ssi->baudclk, baudrate);
809 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
810 struct fsl_ssi_regvals *vals = ssi->regvals;
811 struct regmap *regs = ssi->regs;
817 if (fsl_ssi_is_i2s_clock_provider(ssi)) {
823 if (!(ssi->baudclk_streams & BIT(substream->stream))) {
824 ret = clk_prepare_enable(ssi->baudclk);
828 ssi->baudclk_streams |= BIT(substream->stream);
838 if (ssi->streams && ssi->synchronous)
841 if (!fsl_ssi_is_ac97(ssi)) {
843 * Keep the ssi->i2s_net intact while having a local variable
845 * ssi->i2s_net will lose the settings for regular use cases.
847 u8 i2s_net = ssi->i2s_net;
850 if (fsl_ssi_is_i2s_bc_fp(ssi) && sample_size == 16)
862 tx2 = tx || ssi->synchronous;
865 if (ssi->use_dyna_fifo) {
867 ssi->audio_config[0].n_fifos_dst = 1;
868 ssi->audio_config[1].n_fifos_src = 1;
874 ssi->audio_config[0].n_fifos_dst = 2;
875 ssi->audio_config[1].n_fifos_src = 2;
881 ssi->dma_params_tx.peripheral_config = &ssi->audio_config[0];
882 ssi->dma_params_tx.peripheral_size = sizeof(ssi->audio_config[0]);
883 ssi->dma_params_rx.peripheral_config = &ssi->audio_config[1];
884 ssi->dma_params_rx.peripheral_size = sizeof(ssi->audio_config[1]);
894 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
896 if (fsl_ssi_is_i2s_clock_provider(ssi) &&
897 ssi->baudclk_streams & BIT(substream->stream)) {
898 clk_disable_unprepare(ssi->baudclk);
899 ssi->baudclk_streams &= ~BIT(substream->stream);
905 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
910 ssi->dai_fmt = fmt;
919 ssi->i2s_net = SSI_SCR_NET;
924 if (IS_ERR(ssi->baudclk)) {
925 dev_err(ssi->dev,
931 ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
934 ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
940 slots = ssi->slots ? : 2;
941 regmap_update_bits(ssi->regs, REG_SSI_STCCR,
943 regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
969 scr |= ssi->i2s_net;
1015 if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
1023 regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
1024 regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
1028 regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
1040 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1043 if (fsl_ssi_is_ac97(ssi))
1046 return _fsl_ssi_set_dai_fmt(ssi, fmt);
1060 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1061 struct regmap *regs = ssi->regs;
1071 if (ssi->i2s_net && slots < 2) {
1092 ssi->slot_width = slot_width;
1093 ssi->slots = slots;
1111 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
1125 if (tx && fsl_ssi_is_ac97(ssi))
1126 fsl_ssi_tx_ac97_saccst_setup(ssi);
1127 fsl_ssi_config_enable(ssi, tx);
1133 fsl_ssi_config_disable(ssi, tx);
1145 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1147 if (ssi->soc->imx && ssi->use_dma)
1148 snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
1149 &ssi->dma_params_rx);
1184 .name = "fsl-ssi",
1287 * @ssi: SSI context
1289 static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
1291 u32 wm = ssi->fifo_watermark;
1294 fsl_ssi_setup_regvals(ssi);
1297 regmap_write(ssi->regs, REG_SSI_SFCSR,
1302 if (ssi->use_dual_fifo)
1303 regmap_update_bits(ssi->regs, REG_SSI_SCR,
1307 if (fsl_ssi_is_ac97(ssi)) {
1308 _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
1309 fsl_ssi_setup_ac97(ssi);
1317 * @ssi: SSI context
1319 static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
1322 if (fsl_ssi_is_ac97(ssi)) {
1324 regmap_update_bits(ssi->regs, REG_SSI_SCR,
1327 regmap_write(ssi->regs, REG_SSI_SACNT, 0);
1329 regmap_write(ssi->regs, REG_SSI_SOR, 0);
1331 regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
1347 struct fsl_ssi *ssi, void __iomem *iomem)
1353 if (ssi->has_ipg_clk_name)
1354 ssi->clk = devm_clk_get(dev, "ipg");
1356 ssi->clk = devm_clk_get(dev, NULL);
1357 if (IS_ERR(ssi->clk)) {
1358 ret = PTR_ERR(ssi->clk);
1364 if (!ssi->has_ipg_clk_name) {
1365 ret = clk_prepare_enable(ssi->clk);
1373 ssi->baudclk = devm_clk_get(dev, "baud");
1374 if (IS_ERR(ssi->baudclk))
1376 PTR_ERR(ssi->baudclk));
1378 ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
1379 ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
1380 ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
1381 ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
1384 if (ssi->use_dual_fifo || ssi->use_dyna_fifo) {
1385 ssi->dma_params_tx.maxburst &= ~0x1;
1386 ssi->dma_params_rx.maxburst &= ~0x1;
1389 if (!ssi->use_dma) {
1394 ssi->fiq_params.irq = ssi->irq;
1395 ssi->fiq_params.base = iomem;
1396 ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
1397 ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
1399 ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
1411 if (!ssi->has_ipg_clk_name)
1412 clk_disable_unprepare(ssi->clk);
1417 static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
1419 if (!ssi->use_dma)
1421 if (!ssi->has_ipg_clk_name)
1422 clk_disable_unprepare(ssi->clk);
1425 static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
1427 struct device *dev = ssi->dev;
1436 ssi->has_ipg_clk_name = ret >= 0;
1441 ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
1443 ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
1448 strcpy(ssi->card_name, "ac97-codec");
1449 } else if (!of_property_read_bool(np, "fsl,ssi-asynchronous")) {
1459 ssi->synchronous = true;
1463 ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
1468 ssi->fifo_depth = be32_to_cpup(iprop);
1470 ssi->fifo_depth = 8;
1474 if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
1475 ssi->use_dual_fifo = true;
1477 if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1478 ssi->use_dyna_fifo = true;
1487 if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
1496 snprintf(ssi->card_name, sizeof(ssi->card_name),
1498 make_lowercase(ssi->card_name);
1499 ssi->card_idx = 0;
1509 struct fsl_ssi *ssi;
1514 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
1515 if (!ssi)
1518 ssi->dev = dev;
1519 ssi->soc = of_device_get_match_data(&pdev->dev);
1522 ret = fsl_ssi_probe_from_dt(ssi);
1526 if (fsl_ssi_is_ac97(ssi)) {
1527 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
1529 fsl_ac97_data = ssi;
1531 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
1534 ssi->cpu_dai_drv.name = dev_name(dev);
1539 ssi->ssi_phys = res->start;
1541 if (ssi->soc->imx21regs) {
1548 if (ssi->has_ipg_clk_name)
1549 ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
1552 ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config);
1553 if (IS_ERR(ssi->regs)) {
1555 return PTR_ERR(ssi->regs);
1558 ssi->irq = platform_get_irq(pdev, 0);
1559 if (ssi->irq < 0)
1560 return ssi->irq;
1563 if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
1564 ssi->cpu_dai_drv.symmetric_rate = 1;
1565 ssi->cpu_dai_drv.symmetric_channels = 1;
1566 ssi->cpu_dai_drv.symmetric_sample_bits = 1;
1575 switch (ssi->fifo_depth) {
1585 ssi->fifo_watermark = 8;
1586 ssi->dma_maxburst = 8;
1591 ssi->fifo_watermark = ssi->fifo_depth - 2;
1592 ssi->dma_maxburst = ssi->fifo_depth - 2;
1596 dev_set_drvdata(dev, ssi);
1598 if (ssi->soc->imx) {
1599 ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
1604 if (fsl_ssi_is_ac97(ssi)) {
1605 mutex_init(&ssi->ac97_reg_lock);
1614 &ssi->cpu_dai_drv, 1);
1620 if (ssi->use_dma) {
1621 ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
1622 dev_name(dev), ssi);
1624 dev_err(dev, "failed to claim irq %u\n", ssi->irq);
1629 fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
1632 fsl_ssi_hw_init(ssi);
1635 if (ssi->card_name[0]) {
1643 if (fsl_ssi_is_ac97(ssi))
1646 ssi->card_pdev = platform_device_register_data(parent,
1647 ssi->card_name, ssi->card_idx, NULL, 0);
1648 if (IS_ERR(ssi->card_pdev)) {
1649 ret = PTR_ERR(ssi->card_pdev);
1651 ssi->card_name, ret);
1659 fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1661 if (fsl_ssi_is_ac97(ssi))
1664 if (fsl_ssi_is_ac97(ssi))
1665 mutex_destroy(&ssi->ac97_reg_lock);
1667 if (ssi->soc->imx)
1668 fsl_ssi_imx_clean(pdev, ssi);
1675 struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
1677 fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1679 if (ssi->card_pdev)
1680 platform_device_unregister(ssi->card_pdev);
1683 fsl_ssi_hw_clean(ssi);
1685 if (ssi->soc->imx)
1686 fsl_ssi_imx_clean(pdev, ssi);
1688 if (fsl_ssi_is_ac97(ssi)) {
1690 mutex_destroy(&ssi->ac97_reg_lock);
1697 struct fsl_ssi *ssi = dev_get_drvdata(dev);
1698 struct regmap *regs = ssi->regs;
1700 regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
1701 regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
1711 struct fsl_ssi *ssi = dev_get_drvdata(dev);
1712 struct regmap *regs = ssi->regs;
1719 ssi->regcache_sfcsr);
1720 regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
1732 .name = "fsl-ssi-dai",
1742 MODULE_ALIAS("platform:fsl-ssi-dai");