Lines Matching refs:TX
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
57 #define TX 1
212 * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
215 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
223 * @regvals: Specific RX/TX register settings
243 * @fifo_watermark or fewer words in TX fifo or
407 int dir = tx ? TX : RX;
427 srcr = vals[RX].srcr | vals[TX].srcr;
428 stcr = vals[RX].stcr | vals[TX].stcr;
429 sier = vals[RX].sier | vals[TX].sier;
453 /* Enable SSI first to send TX DMA request */
457 /* Busy wait until TX FIFO not empty -- DMA working */
466 dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
511 int adir = tx ? RX : TX;
512 int dir = tx ? TX : RX;
593 vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
594 vals[TX].stcr = SSI_STCR_TFEN0;
595 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
599 vals[RX].scr = vals[TX].scr = 0;
603 vals[TX].stcr |= SSI_STCR_TFEN1;
608 vals[TX].sier |= SSI_SIER_TDMAE;
611 vals[TX].sier |= SSI_SIER_TIE;
799 * running in synchronous mode (both TX and RX use STCCR), it is not
870 vals[TX].stcr &= ~SSI_STCR_TFEN1;
872 vals[TX].scr &= ~SSI_SCR_TCH_EN;
877 vals[TX].stcr |= SSI_STCR_TFEN1;
879 vals[TX].scr |= SSI_SCR_TCH_EN;
1052 * @tx_mask: mask for TX
1123 * To be safe, configure SACCST right before TX starts.
1570 * Configure TX and RX DMA watermarks -- when to send a DMA request
1578 * Set to 8 as a balanced configuration -- When TX FIFO has 8
1581 * transaction before TX FIFO underruns; Same applies to RX.