Lines Matching refs:RX
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
56 #define RX 0
212 * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
215 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
223 * @regvals: Specific RX/TX register settings
244 * @fifo_watermark or more empty words in RX fifo.
407 int dir = tx ? TX : RX;
427 srcr = vals[RX].srcr | vals[TX].srcr;
428 stcr = vals[RX].stcr | vals[TX].stcr;
429 sier = vals[RX].sier | vals[TX].sier;
511 int adir = tx ? RX : TX;
512 int dir = tx ? TX : RX;
590 vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
591 vals[RX].srcr = SSI_SRCR_RFEN0;
592 vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
599 vals[RX].scr = vals[TX].scr = 0;
602 vals[RX].srcr |= SSI_SRCR_RFEN1;
607 vals[RX].sier |= SSI_SIER_RDMAE;
610 vals[RX].sier |= SSI_SIER_RIE;
775 /* STCCR is used for RX in synchronous mode */
799 * running in synchronous mode (both TX and RX use STCCR), it is not
869 vals[RX].srcr &= ~SSI_SRCR_RFEN1;
871 vals[RX].scr &= ~SSI_SCR_TCH_EN;
876 vals[RX].srcr |= SSI_SRCR_RFEN1;
878 vals[RX].scr |= SSI_SCR_TCH_EN;
1053 * @rx_mask: mask for RX
1451 * In synchronous mode, STCK and STFS ports are used by RX
1570 * Configure TX and RX DMA watermarks -- when to send a DMA request
1581 * transaction before TX FIFO underruns; Same applies to RX.