Lines Matching refs:set
54 * so the driver shouldn't set root clock rate
475 * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP
579 dev_err(&pdev->dev, "failed to set tx clock rate\n");
589 /* set fs field in consumer channel status */
599 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
721 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
1000 bool set = (ucontrol->value.integer.value[0] != 0);
1008 if (priv->bypass == set)
1018 if (set) {
1038 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1);
1040 priv->bypass = set;
1225 /* User bit sync mode set/get controller */