Lines Matching refs:esai_priv
100 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
101 struct platform_device *pdev = esai_priv->pdev;
105 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
106 regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
109 esai_priv->soc->reset_at_xrun) {
111 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
113 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
115 schedule_work(&esai_priv->work);
168 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
234 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
243 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
262 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
263 struct clk *clksrc = esai_priv->extalclk;
264 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous);
277 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
281 esai_priv->sck_div[tx] = true;
284 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
293 clksrc = esai_priv->fsysclk;
299 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI;
328 if (ratio == 1 && clksrc == esai_priv->extalclk) {
343 esai_priv->sck_div[tx] = false;
346 esai_priv->hck_dir[tx] = dir;
347 esai_priv->hck_rate[tx] = freq;
349 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
364 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
365 u32 hck_rate = esai_priv->hck_rate[tx];
370 if (esai_priv->consumer_mode || esai_priv->sck_rate[tx] == freq)
388 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
394 esai_priv->sck_div[tx] ? 0 : ratio);
399 esai_priv->sck_rate[tx] = freq;
407 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
409 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
412 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
415 esai_priv->slot_width = slot_width;
416 esai_priv->slots = slots;
417 esai_priv->tx_mask = tx_mask;
418 esai_priv->rx_mask = rx_mask;
425 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
479 esai_priv->consumer_mode = false;
484 esai_priv->consumer_mode = true;
500 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
501 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
505 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
506 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
514 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
518 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
519 ESAI_SAICR_SYNC, esai_priv->synchronous ?
523 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
525 ESAI_xCCR_xDC(esai_priv->slots));
526 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
528 ESAI_xCCR_xDC(esai_priv->slots));
539 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
543 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
549 if (esai_priv->slot_width)
550 slot_width = esai_priv->slot_width;
552 bclk = params_rate(params) * slot_width * esai_priv->slots;
554 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk);
561 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
563 if (!tx && esai_priv->synchronous)
564 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val);
567 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
571 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
576 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
579 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
582 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
586 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
588 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
593 static int fsl_esai_hw_init(struct fsl_esai *esai_priv)
595 struct platform_device *pdev = esai_priv->pdev;
599 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
611 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
619 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
621 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
627 static int fsl_esai_register_restore(struct fsl_esai *esai_priv)
632 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR,
634 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR,
637 regcache_mark_dirty(esai_priv->regmap);
638 ret = regcache_sync(esai_priv->regmap);
643 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
644 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
649 static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)
651 u8 i, channels = esai_priv->channels[tx];
652 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
655 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
660 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
674 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
677 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
679 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
681 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
685 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
689 static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)
691 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
694 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
696 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
698 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
702 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
704 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
710 struct fsl_esai *esai_priv = container_of(work, struct fsl_esai, work);
715 spin_lock_irqsave(&esai_priv->lock, lock_flags);
717 regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr);
718 regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr);
723 fsl_esai_trigger_stop(esai_priv, tx);
724 fsl_esai_trigger_stop(esai_priv, rx);
727 fsl_esai_hw_init(esai_priv);
730 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
732 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
736 fsl_esai_register_restore(esai_priv);
739 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
741 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
743 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
745 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
750 fsl_esai_trigger_start(esai_priv, tx);
752 fsl_esai_trigger_start(esai_priv, rx);
754 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
760 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
764 esai_priv->channels[tx] = substream->runtime->channels;
770 spin_lock_irqsave(&esai_priv->lock, lock_flags);
771 fsl_esai_trigger_start(esai_priv, tx);
772 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
777 spin_lock_irqsave(&esai_priv->lock, lock_flags);
778 fsl_esai_trigger_stop(esai_priv, tx);
779 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
790 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
792 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
793 &esai_priv->dma_params_rx);
957 struct fsl_esai *esai_priv;
963 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
964 if (!esai_priv)
967 esai_priv->pdev = pdev;
968 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np);
970 esai_priv->soc = of_device_get_match_data(&pdev->dev);
977 esai_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_esai_regmap_config);
978 if (IS_ERR(esai_priv->regmap)) {
980 PTR_ERR(esai_priv->regmap));
981 return PTR_ERR(esai_priv->regmap);
984 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
985 if (IS_ERR(esai_priv->coreclk)) {
987 PTR_ERR(esai_priv->coreclk));
988 return PTR_ERR(esai_priv->coreclk);
991 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
992 if (IS_ERR(esai_priv->extalclk))
994 PTR_ERR(esai_priv->extalclk));
996 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
997 if (IS_ERR(esai_priv->fsysclk))
999 PTR_ERR(esai_priv->fsysclk));
1001 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1002 if (IS_ERR(esai_priv->spbaclk))
1004 PTR_ERR(esai_priv->spbaclk));
1011 esai_priv->name, esai_priv);
1018 esai_priv->slots = 2;
1021 esai_priv->consumer_mode = true;
1026 esai_priv->fifo_depth = be32_to_cpup(iprop);
1028 esai_priv->fifo_depth = 64;
1030 esai_priv->dma_params_tx.maxburst = 16;
1031 esai_priv->dma_params_rx.maxburst = 16;
1032 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
1033 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
1035 esai_priv->synchronous =
1039 if (esai_priv->synchronous) {
1045 dev_set_drvdata(&pdev->dev, esai_priv);
1046 spin_lock_init(&esai_priv->lock);
1058 ret = fsl_esai_hw_init(esai_priv);
1062 esai_priv->tx_mask = 0xFFFFFFFF;
1063 esai_priv->rx_mask = 0xFFFFFFFF;
1066 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
1067 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
1068 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
1069 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
1092 INIT_WORK(&esai_priv->work, fsl_esai_hw_reset);
1106 struct fsl_esai *esai_priv = platform_get_drvdata(pdev);
1112 cancel_work_sync(&esai_priv->work);