Lines Matching refs:dai
1420 static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute, int direction)
1422 struct snd_soc_component *component = dai->component;
1425 switch (dai->id) {
1441 static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1447 component = dai->component;
1457 dev_err(dai->dev, "Unknown master/slave configuration\n");
1478 dev_err(dai->dev, "Unknown dai format\n");
1545 struct snd_soc_dai *dai)
1558 component = dai->component;
1561 switch (dai->id) {
1608 dev_err(dai->dev, "Unsupported word length %u\n",
1618 dev_err(dai->dev, "Sample rate %d is not supported\n",
1624 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
1625 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1626 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
1631 - wm8995->aifclk[dai->id]);
1634 - wm8995->aifclk[dai->id]);
1642 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1643 dai->id + 1, fs_ratios[best]);
1654 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
1661 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
1662 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1666 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1794 static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
1804 component = dai->component;
1905 static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
1911 component = dai->component;
1914 switch (dai->id) {
1925 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1927 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1928 dai->id + 1, freq);
1931 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK2;
1933 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1934 dai->id + 1, freq);
1937 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
1938 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
1941 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
1942 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
1946 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);