Lines Matching refs:dai
652 static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute, int direction)
654 struct snd_soc_component *component = dai->component;
661 static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
666 component = dai->component;
683 dev_err(dai->dev, "Unknown dai format\n");
698 dev_err(dai->dev, "Unknown master/slave configuration\n");
735 dev_err(dai->dev, "Unknown polarity configuration\n");
748 struct snd_soc_dai *dai)
757 component = dai->component;
778 dev_err(dai->dev, "Unsupported word length %u\n",
799 dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
803 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
804 dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
813 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
818 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
830 dev_err(dai->dev, "No matching BCLK divider found\n");
834 dev_dbg(dai->dev, "BCLK div = %d\n", i);
882 static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
890 component = dai->component;
918 static int wm8985_set_sysclk(struct snd_soc_dai *dai,
924 component = dai->component;
939 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);