Lines Matching refs:x2000
716 #define WM2200_EPD_OUTP_LP_ENA 0x2000 /* EPD_OUTP_LP_ENA */
717 #define WM2200_EPD_OUTP_LP_ENA_MASK 0x2000 /* EPD_OUTP_LP_ENA */
744 #define WM2200_EPD_OUTP_RP_ENA 0x2000 /* EPD_OUTP_RP_ENA */
745 #define WM2200_EPD_OUTP_RP_ENA_MASK 0x2000 /* EPD_OUTP_RP_ENA */
796 #define WM2200_IN1_OSR 0x2000 /* IN1_OSR */
797 #define WM2200_IN1_OSR_MASK 0x2000 /* IN1_OSR */
820 #define WM2200_IN2_OSR 0x2000 /* IN2_OSR */
821 #define WM2200_IN2_OSR_MASK 0x2000 /* IN2_OSR */
844 #define WM2200_IN3_OSR 0x2000 /* IN3_OSR */
845 #define WM2200_IN3_OSR_MASK 0x2000 /* IN3_OSR */
995 #define WM2200_OUT1_OSR 0x2000 /* OUT1_OSR */
996 #define WM2200_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
1021 #define WM2200_OUT2_OSR 0x2000 /* OUT2_OSR */
1022 #define WM2200_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
1122 #define WM2200_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
1123 #define WM2200_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
2493 #define WM2200_GP1_PD 0x2000 /* GP1_PD */
2494 #define WM2200_GP1_PD_MASK 0x2000 /* GP1_PD */
2528 #define WM2200_GP2_PD 0x2000 /* GP2_PD */
2529 #define WM2200_GP2_PD_MASK 0x2000 /* GP2_PD */
2563 #define WM2200_GP3_PD 0x2000 /* GP3_PD */
2564 #define WM2200_GP3_PD_MASK 0x2000 /* GP3_PD */
2598 #define WM2200_GP4_PD 0x2000 /* GP4_PD */
2599 #define WM2200_GP4_PD_MASK 0x2000 /* GP4_PD */
2653 #define WM2200_MCLK2_PD 0x2000 /* MCLK2_PD */
2654 #define WM2200_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */