Lines Matching defs:component
79 struct snd_soc_component *component;
1545 static int wm2200_probe(struct snd_soc_component *component)
1547 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
1549 wm2200->component = component;
1556 struct snd_soc_component *component = dai->component;
1570 dev_err(component->dev, "Unsupported DAI format %d\n",
1589 dev_err(component->dev, "Unsupported master mode %d\n",
1611 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_1, WM2200_AIF1_BCLK_MSTR |
1613 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_2,
1616 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_3,
1619 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_5,
1688 struct snd_soc_component *component = dai->component;
1689 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
1701 dev_dbg(component->dev, "Word length %d bits, frame length %d bits\n",
1710 dev_err(component->dev, "SYSCLK has no rate set\n");
1718 dev_err(component->dev, "Unsupported sample rate: %dHz\n",
1724 dev_dbg(component->dev, "Target BCLK is %dHz, using %dHz SYSCLK\n",
1736 dev_err(component->dev,
1743 dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1744 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_1,
1748 dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1751 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_7,
1754 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_6,
1759 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_9,
1763 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_8,
1767 snd_soc_component_update_bits(component, WM2200_CLOCKING_4,
1773 static int wm2200_set_sysclk(struct snd_soc_component *component, int clk_id,
1776 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
1784 dev_err(component->dev, "Unknown clock %d\n", clk_id);
1795 dev_err(component->dev, "Invalid source %d\n", source);
1805 dev_err(component->dev, "Invalid clock rate: %d\n", freq);
1813 snd_soc_component_update_bits(component, WM2200_CLOCKING_3, WM2200_SYSCLK_FREQ_MASK |
1921 static int wm2200_set_fll(struct snd_soc_component *component, int fll_id, int source,
1924 struct i2c_client *i2c = to_i2c_client(component->dev);
1925 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
1931 dev_dbg(component->dev, "FLL disabled");
1934 pm_runtime_put(component->dev);
1937 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_1,
1948 dev_err(component->dev, "Invalid FLL source %d\n", source);
1957 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_1, WM2200_FLL_ENA, 0);
1959 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_2,
1964 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_3,
1967 snd_soc_component_update_bits(component, WM2200_FLL_EFS_2,
1971 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_3,
1973 snd_soc_component_update_bits(component, WM2200_FLL_EFS_2,
1977 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_4, WM2200_FLL_THETA_MASK,
1979 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_6, WM2200_FLL_N_MASK,
1981 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_7,
1986 snd_soc_component_update_bits(component, WM2200_FLL_EFS_1,
1992 pm_runtime_get_sync(component->dev);
1994 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_1,
2002 snd_soc_component_update_bits(component, WM2200_CLOCKING_3, WM2200_SYSCLK_ENA,
2017 ret = snd_soc_component_read(component,
2020 dev_err(component->dev,
2029 dev_err(component->dev, "FLL lock timed out\n");
2030 pm_runtime_put(component->dev);
2038 dev_dbg(component->dev, "FLL running %dHz->%dHz\n", Fref, Fout);
2045 struct snd_soc_component *component = dai->component;
2046 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
2050 ret = snd_soc_component_read(component, WM2200_GPIO_CTRL_1);
2057 dev_err(component->dev, "Failed to read GPIO 1 config: %d\n", ret);
2060 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_2,