Lines Matching defs:bclk
1557 int lrclk, bclk, fmt_val;
1560 bclk = 0;
1582 bclk |= WM2200_AIF1_BCLK_MSTR;
1586 bclk |= WM2200_AIF1_BCLK_MSTR;
1598 bclk |= WM2200_AIF1_BCLK_INV;
1602 bclk |= WM2200_AIF1_BCLK_INV;
1612 WM2200_AIF1_BCLK_INV, bclk);
1690 int i, bclk, lrclk, wl, fl, sr_code;
1705 bclk = snd_soc_params_to_bclk(params);
1706 if (bclk < 0)
1707 return bclk;
1725 bclk, wm2200->sysclk);
1733 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1738 bclk, wm2200->sysclk);
1742 bclk = i;
1743 dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1745 WM2200_AIF1_BCLK_DIV_MASK, bclk);
1747 lrclk = bclk_rates[bclk] / params_rate(params);
1748 dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);