Lines Matching defs:val
1385 int val;
1388 &val);
1391 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1462 int rc, val;
1482 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1483 if (rc || (!(val & 0x01)))
1484 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1485 __func__, val, rc);
1571 int val, j;
1578 val = snd_soc_component_read(component,
1582 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
2132 int ret, val;
2134 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2135 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2285 unsigned int val, int_val = 0;
2292 regmap_read(wcd->if_regmap, i, &val);
2293 status |= ((u32)val << (8 * j));
2306 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2307 if (val) {
2317 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2320 (tx ? "TX" : "RX"), port_id, val);
2322 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2325 (tx ? "TX" : "RX"), port_id, val);
2327 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2328 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2344 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2347 (tx ? "TX" : "RX"), port_id, val);
2393 u8 val;
2396 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2,
2398 if (val == WCD934X_MICB_ENABLE)
2650 int val, val1;
2660 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val);
2661 if (val & 0x80)
2664 val = val << 0x8;
2666 val |= val1;
2668 x1 = WCD934X_MBHC_GET_X1(val);
2669 c1 = WCD934X_MBHC_GET_C1(val);
2692 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val);
2694 val = val << 0x08;
2695 val |= val1;
2696 x1 = WCD934X_MBHC_GET_X1(val);
3100 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
3105 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
3109 val);
3417 int reg, val;
3420 val = ucontrol->value.enumerated.item[0];
3431 if (val)
3448 unsigned int val;
3454 val = ucontrol->value.enumerated.item[0];
3455 if (val > e->items - 1)
3492 mic_sel = val ? 0x0 : 0x1;
4148 unsigned int val = 0;
4161 regmap_read(wcd->if_regmap, reg, &val);
4162 if (!(val & BIT(port_num % 8)))
4164 val | BIT(port_num % 8));
4362 int val = 0;
4378 val = snd_soc_component_read(comp, gain_reg);
4379 val += offset_val;
4380 snd_soc_component_write(comp, gain_reg, val);
5122 u8 val;
5128 val = set ? mask : 0x00;
5134 mask, val);
5139 mask, val);