Lines Matching defs:IIR1
163 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
173 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
183 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
411 IIR1,
624 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
3612 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
3614 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
3616 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
3618 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
4056 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
4059 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
4062 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
4065 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
4097 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4099 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4101 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4103 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4105 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4123 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
4124 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
4125 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
4126 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
4127 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
5370 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
5371 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
5372 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
5373 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
5378 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
5824 {"SRC1", NULL, "IIR1"},