Lines Matching refs:val
67 unsigned int val;
70 ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
74 return !!(val & AIC32X4_PLLEN);
81 unsigned int val;
84 ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
87 settings->r = val & AIC32X4_PLL_R_MASK;
88 settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;
90 ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);
93 settings->j = val;
95 ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);
98 settings->d = val << 8;
100 ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val);
103 settings->d |= val;
257 unsigned int val;
259 regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
261 return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT;
288 unsigned int val;
290 regmap_read(mux->regmap, AIC32X4_CLKMUX, &val);
292 return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT;
348 unsigned int val;
351 err = regmap_read(div->regmap, div->reg, &val);
355 val &= AIC32X4_DIV_MASK;
356 if (!val)
357 val = AIC32X4_DIV_MAX;
359 return DIV_ROUND_UP(parent_rate, val);
381 unsigned int val;
383 regmap_read(mux->regmap, AIC32X4_IFACE3, &val);
385 return val & AIC32X4_BDIVCLK_MASK;