Lines Matching refs:settings
26 * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
78 struct clk_aic32x4_pll_muldiv *settings)
87 settings->r = val & AIC32X4_PLL_R_MASK;
88 settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;
93 settings->j = val;
98 settings->d = val << 8;
103 settings->d |= val;
109 struct clk_aic32x4_pll_muldiv *settings)
115 AIC32X4_PLL_R_MASK, settings->r);
121 settings->p << AIC32X4_PLL_P_SHIFT);
125 ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);
129 ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));
132 ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));
140 struct clk_aic32x4_pll_muldiv *settings,
148 rate = (u64) parent_rate * settings->r *
149 ((settings->j * 10000) + settings->d);
151 return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);
154 static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
159 settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1;
160 if (settings->p > 8)
168 multiplier = (u64) rate * settings->p * 10000;
175 settings->r = ((u32) multiplier / 640000) + 1;
176 if (settings->r > 4)
178 do_div(multiplier, settings->r);
187 settings->j = (u32) multiplier / 10000;
188 settings->d = (u32) multiplier % 10000;
197 struct clk_aic32x4_pll_muldiv settings;
200 ret = clk_aic32x4_pll_get_muldiv(pll, &settings);
204 return clk_aic32x4_pll_calc_rate(&settings, parent_rate);
210 struct clk_aic32x4_pll_muldiv settings;
213 ret = clk_aic32x4_pll_calc_muldiv(&settings, req->rate, req->best_parent_rate);
217 req->rate = clk_aic32x4_pll_calc_rate(&settings, req->best_parent_rate);
227 struct clk_aic32x4_pll_muldiv settings;
230 ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate);
234 ret = clk_aic32x4_pll_set_muldiv(pll, &settings);