Lines Matching refs:lrck
1230 ref = 256 * rt5682s->lrck[RT5682S_AIF2];
1232 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
1302 pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]);
1308 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n",
1309 rt5682s->lrck[id], pre_div, id);
2068 rt5682s->lrck[dai->id] = params_rate(params);
2551 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
2603 if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
2604 rt5682s->lrck[RT5682S_AIF1] != CLK_44) {
2610 return rt5682s->lrck[RT5682S_AIF1];
2677 rt5682s->lrck[RT5682S_AIF1] = rate;
2859 rt5682s->lrck[RT5682S_AIF1] = CLK_48;