Lines Matching defs:rate
1048 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1091 "sysclk rate %d is too low\n", rt5682s->sysclk);
1108 "sysclk rate %d is too high\n", rt5682s->sysclk);
1113 static int get_clk_info(int sclk, int rate)
1118 if (sclk <= 0 || rate <= 0)
1121 rate = rate << 8;
1123 if (sclk == rate * pd[i])
1208 /* select over sample rate */
2549 /* Only need to power on PLLB due to the rate set restriction */
2601 * Only accept to set wclk rate to 44.1k or 48kHz.
2613 static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2624 * Only accept to set wclk rate to 44.1k or 48kHz.
2627 if (rate != CLK_48 && rate != CLK_44) {
2630 rate = CLK_48;
2633 return rate;
2636 static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2651 * it is fixed or set to 48MHz before setting wclk rate. It's a
2667 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2670 clk_pll2_fout = rate * 512;
2677 rt5682s->lrck[RT5682S_AIF1] = rate;
2706 static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
2711 factor = rate / parent_rate;
2722 static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2735 * some rounding down based on the parent WCLK rate
2739 factor = rt5682s_bclk_get_factor(rate, *parent_rate);
2744 static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2756 factor = rt5682s_bclk_get_factor(rate, parent_rate);
2968 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",