Lines Matching defs:rate
831 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1224 "sysclk rate %d is too low\n", rt5682->sysclk);
1242 "sysclk rate %d is too high\n", rt5682->sysclk);
1308 /* select over sample rate */
2664 * Only accept to set wclk rate to 44.1k or 48kHz.
2676 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2687 * Only accept to set wclk rate to 44.1k or 48kHz.
2690 if (rate != CLK_48 && rate != CLK_44) {
2693 rate = CLK_48;
2696 return rate;
2699 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2718 * it is fixed or set to 48MHz before setting wclk rate. It's a
2734 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2737 clk_pll2_out = rate * 512;
2744 rt5682->lrck[RT5682_AIF1] = rate;
2746 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2780 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2785 factor = rate / parent_rate;
2796 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2810 * some rounding down based on the parent WCLK rate
2814 factor = rt5682_bclk_get_factor(rate, *parent_rate);
2819 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2834 factor = rt5682_bclk_get_factor(rate, parent_rate);
3091 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",