Lines Matching refs:x7
375 #define RT5677_ST_HPF_SEL_MASK (0x7 << 13)
379 #define RT5677_ST_SEL_MASK (0x7 << 9)
397 #define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
401 #define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
405 #define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4)
409 #define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0)
439 #define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4)
443 #define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0)
607 #define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
822 #define RT5677_IF1_ADC_CTRL_MASK (0x7 << 0)
826 #define RT5677_IF1_DAC0_MASK (0x7 << 12)
828 #define RT5677_IF1_DAC1_MASK (0x7 << 8)
830 #define RT5677_IF1_DAC2_MASK (0x7 << 4)
832 #define RT5677_IF1_DAC3_MASK (0x7 << 0)
836 #define RT5677_IF1_DAC4_MASK (0x7 << 12)
838 #define RT5677_IF1_DAC5_MASK (0x7 << 8)
840 #define RT5677_IF1_DAC6_MASK (0x7 << 4)
842 #define RT5677_IF1_DAC7_MASK (0x7 << 0)
868 #define RT5677_IF2_ADC_CTRL_MASK (0x7 << 0)
872 #define RT5677_IF2_DAC0_MASK (0x7 << 12)
874 #define RT5677_IF2_DAC1_MASK (0x7 << 8)
876 #define RT5677_IF2_DAC2_MASK (0x7 << 4)
878 #define RT5677_IF2_DAC3_MASK (0x7 << 0)
882 #define RT5677_IF2_DAC4_MASK (0x7 << 12)
884 #define RT5677_IF2_DAC5_MASK (0x7 << 8)
886 #define RT5677_IF2_DAC6_MASK (0x7 << 4)
888 #define RT5677_IF2_DAC7_MASK (0x7 << 0)
924 #define RT5677_DMIC_CLK_MASK (0x7 << 5)
1060 #define RT5677_LDO2_SEL_MASK (0x7 << 4)
1062 #define RT5677_LDO1_SEL_MASK (0x7 << 0)
1202 #define RT5677_I2S_PD1_MASK (0x7 << 12)
1211 #define RT5677_I2S_PD1_16 (0x7 << 12)
1216 #define RT5677_I2S_PD2_MASK (0x7 << 8)
1225 #define RT5677_I2S_PD2_16 (0x7 << 8)
1230 #define RT5677_I2S_PD3_MASK (0x7 << 4)
1239 #define RT5677_I2S_PD3_16 (0x7 << 4)
1244 #define RT5677_I2S_PD4_MASK (0x7 << 0)
1253 #define RT5677_I2S_PD4_16 (0x7 << 0)
1256 #define RT5677_I2S_PD5_MASK (0x7 << 12)
1265 #define RT5677_I2S_PD5_16 (0x7 << 12)
1266 #define RT5677_I2S_PD6_MASK (0x7 << 8)
1275 #define RT5677_I2S_PD6_16 (0x7 << 8)
1276 #define RT5677_I2S_PD7_MASK (0x7 << 4)
1285 #define RT5677_I2S_PD7_16 (0x7 << 4)
1286 #define RT5677_I2S_PD8_MASK (0x7 << 0)
1295 #define RT5677_I2S_PD8_16 (0x7 << 0)
1310 #define RT5677_DSP_BUS_PD_MASK (0x7 << 0)
1319 #define RT5677_DSP_BUS_PD_16 (0x7 << 0)
1349 #define RT5677_PLL1_SRC_MASK (0x7 << 11)
1382 #define RT5677_PLL2_SRC_MASK (0x7 << 12)
1491 #define RT5677_IB01_SRC_MASK (0x7 << 12)
1493 #define RT5677_IB23_SRC_MASK (0x7 << 8)
1495 #define RT5677_IB45_SRC_MASK (0x7 << 4)
1497 #define RT5677_IB6_SRC_MASK (0x7 << 0)
1501 #define RT5677_IB7_SRC_MASK (0x7 << 12)
1503 #define RT5677_IB8_SRC_MASK (0x7 << 8)
1505 #define RT5677_IB9_SRC_MASK (0x7 << 4)