Lines Matching defs:rt5677
3 * rt5677.c -- RT5677 ALSA SoC audio codec driver
34 #include "rt5677.h"
35 #include "rt5677-spi.h"
553 * @rt5677: Private Data.
560 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
563 struct snd_soc_component *component = rt5677->component;
566 mutex_lock(&rt5677->dsp_cmd_lock);
568 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
575 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
582 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
589 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
596 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
604 mutex_unlock(&rt5677->dsp_cmd_lock);
611 * @rt5677: Private Data.
619 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
621 struct snd_soc_component *component = rt5677->component;
625 mutex_lock(&rt5677->dsp_cmd_lock);
627 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
634 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
641 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
648 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
649 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
653 mutex_unlock(&rt5677->dsp_cmd_lock);
660 * @rt5677: Private Data.
667 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
670 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
676 * @rt5677: Private Data
684 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
686 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
694 static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on)
697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
699 rt5677->is_dsp_mode = true;
701 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
703 rt5677->is_dsp_mode = false;
707 static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677)
710 snd_soc_component_get_dapm(rt5677->component);
719 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
723 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
727 regmap_write(rt5677->regmap, RT5677_GLB_CLK2,
731 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f);
733 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5);
738 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4,
751 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1,
764 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4,
770 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
777 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
787 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
800 regmap_write(rt5677->regmap, RT5677_PWR_DSP1,
811 static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf,
814 struct snd_soc_component *component = rt5677->component;
855 static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677)
858 struct device *dev = rt5677->component->dev;
869 ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size);
876 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
877 rt5677->dsp_vad_en_request = on;
878 rt5677->dsp_vad_en = on;
883 schedule_delayed_work(&rt5677->dsp_work, 0);
889 struct rt5677_priv *rt5677 =
892 bool enable = rt5677->dsp_vad_en;
896 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n",
912 rt5677_set_vad_source(rt5677);
913 rt5677_set_dsp_mode(rt5677, true);
917 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val);
923 dev_err(rt5677->component->dev, "DSP Boot Timed Out!");
928 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
930 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
932 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
935 rt5677_load_dsp_from_file(rt5677);
938 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
944 mutex_lock(&rt5677->irq_lock);
946 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
949 rt5677_set_dsp_mode(rt5677, false);
952 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184);
955 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
958 mutex_unlock(&rt5677->irq_lock);
982 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
984 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request;
1089 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1092 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
1098 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
1107 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1110 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
1122 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1189 regmap_read(rt5677->regmap, reg, &val);
1205 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1207 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1230 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1278 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1307 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1336 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1353 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1370 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1399 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1410 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1415 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1421 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1427 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1433 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1439 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1445 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
2571 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2575 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2580 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2595 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2599 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2604 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2619 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2623 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2627 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2641 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2645 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2649 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2663 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2667 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2674 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2690 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2695 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2697 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2713 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2718 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2720 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2736 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2741 !rt5677->is_vref_slow) {
2743 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2746 rt5677->is_vref_slow = true;
4291 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4295 rt5677->lrck[dai->id] = params_rate(params);
4296 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4299 rt5677->sysclk, rt5677->lrck[dai->id]);
4308 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4311 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4335 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4337 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4343 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4345 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4352 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4354 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4361 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4363 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4376 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4381 rt5677->master[dai->id] = 1;
4385 rt5677->master[dai->id] = 0;
4419 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4424 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4429 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4434 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4450 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4453 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4470 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4472 rt5677->sysclk = freq;
4473 rt5677->sysclk_src = clk_id;
4503 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4507 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4508 freq_out == rt5677->pll_out)
4514 rt5677->pll_in = 0;
4515 rt5677->pll_out = 0;
4516 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4523 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4532 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4536 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4540 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4544 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4566 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4568 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4572 rt5677->pll_in = freq_in;
4573 rt5677->pll_out = freq_out;
4574 rt5677->pll_src = source;
4583 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4624 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4626 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4630 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4632 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4645 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4656 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4660 regmap_update_bits(rt5677->regmap,
4663 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4669 rt5677->is_vref_slow = false;
4670 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4672 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4679 rt5677->dsp_vad_en_request) {
4681 rt5677->dsp_vad_en = true;
4683 schedule_delayed_work(&rt5677->dsp_work,
4689 flush_delayed_work(&rt5677->dsp_work);
4690 if (rt5677->is_dsp_mode) {
4692 rt5677->dsp_vad_en = false;
4693 schedule_delayed_work(&rt5677->dsp_work, 0);
4694 flush_delayed_work(&rt5677->dsp_work);
4697 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4698 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4699 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1,
4702 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4704 regmap_update_bits(rt5677->regmap,
4707 if (rt5677->dsp_vad_en)
4718 static int rt5677_update_gpio_bits(struct rt5677_priv *rt5677, unsigned offset, int m, int v)
4724 return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift);
4730 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4734 rt5677_update_gpio_bits(rt5677, offset, m, level);
4740 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4745 return rt5677_update_gpio_bits(rt5677, offset, m, v);
4750 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4753 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4762 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4766 return rt5677_update_gpio_bits(rt5677, offset, m, v);
4775 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4783 regmap_update_bits(rt5677->regmap,
4791 regmap_update_bits(rt5677->regmap,
4804 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4807 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4808 (rt5677->pdata.jd1_gpio == 2 &&
4810 (rt5677->pdata.jd1_gpio == 3 &&
4813 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4814 (rt5677->pdata.jd2_gpio == 2 &&
4816 (rt5677->pdata.jd2_gpio == 3 &&
4819 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4821 (rt5677->pdata.jd3_gpio == 2 &&
4823 (rt5677->pdata.jd3_gpio == 3 &&
4830 return irq_create_mapping(rt5677->domain, irq);
4846 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4849 rt5677->gpio_chip = rt5677_template_chip;
4850 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4851 rt5677->gpio_chip.parent = &i2c->dev;
4852 rt5677->gpio_chip.base = -1;
4854 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4861 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4863 gpiochip_remove(&rt5677->gpio_chip);
4866 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4883 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4886 rt5677->component = component;
4888 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4900 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4902 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
4906 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4908 mutex_init(&rt5677->dsp_cmd_lock);
4909 mutex_init(&rt5677->dsp_pri_lock);
4916 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4918 cancel_delayed_work_sync(&rt5677->dsp_work);
4920 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4921 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4922 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4928 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4930 if (rt5677->irq) {
4931 cancel_delayed_work_sync(&rt5677->resume_irq_check);
4932 disable_irq(rt5677->irq);
4935 if (!rt5677->dsp_vad_en) {
4936 regcache_cache_only(rt5677->regmap, true);
4937 regcache_mark_dirty(rt5677->regmap);
4939 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4940 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4948 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4950 if (!rt5677->dsp_vad_en) {
4951 rt5677->pll_src = 0;
4952 rt5677->pll_in = 0;
4953 rt5677->pll_out = 0;
4954 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4955 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4956 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4959 regcache_cache_only(rt5677->regmap, false);
4960 regcache_sync(rt5677->regmap);
4963 if (rt5677->irq) {
4964 enable_irq(rt5677->irq);
4965 schedule_delayed_work(&rt5677->resume_irq_check, 0);
4978 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4980 if (rt5677->is_dsp_mode) {
4982 mutex_lock(&rt5677->dsp_pri_lock);
4983 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4985 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4986 mutex_unlock(&rt5677->dsp_pri_lock);
4988 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4991 regmap_read(rt5677->regmap_physical, reg, val);
5000 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
5002 if (rt5677->is_dsp_mode) {
5004 mutex_lock(&rt5677->dsp_pri_lock);
5005 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
5007 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
5009 mutex_unlock(&rt5677->dsp_pri_lock);
5011 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
5014 regmap_write(rt5677->regmap_physical, reg, val);
5039 .name = "rt5677-aif1",
5058 .name = "rt5677-aif2",
5077 .name = "rt5677-aif3",
5096 .name = "rt5677-aif4",
5115 .name = "rt5677-slimbus",
5134 .name = "rt5677-dspbuffer",
5198 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 },
5209 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5214 rt5677->pdata.in1_diff =
5218 rt5677->pdata.in2_diff =
5222 rt5677->pdata.lout1_diff =
5226 rt5677->pdata.lout2_diff =
5230 rt5677->pdata.lout3_diff =
5235 rt5677->pdata.gpio_config,
5240 rt5677->pdata.dmic2_clk_pin = val;
5244 rt5677->pdata.jd1_gpio = val;
5248 rt5677->pdata.jd2_gpio = val;
5252 rt5677->pdata.jd3_gpio = val;
5279 static bool rt5677_check_hotword(struct rt5677_priv *rt5677)
5283 if (!rt5677->is_dsp_mode)
5286 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio))
5294 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5303 struct rt5677_priv *rt5677 = data;
5307 mutex_lock(&rt5677->irq_lock);
5325 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq);
5327 dev_err(rt5677->dev, "failed reading IRQ status: %d\n",
5336 virq = irq_find_mapping(rt5677->domain, i);
5352 if (!irq_fired && !rt5677_check_hotword(rt5677))
5355 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq);
5357 dev_err(rt5677->dev, "failed updating IRQ status: %d\n",
5364 mutex_unlock(&rt5677->irq_lock);
5374 struct rt5677_priv *rt5677 =
5382 rt5677_irq(0, rt5677);
5393 mutex_lock(&rt5677->irq_lock);
5395 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) {
5396 virq = irq_find_mapping(rt5677->domain, i);
5401 mutex_unlock(&rt5677->irq_lock);
5406 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5408 mutex_lock(&rt5677->irq_lock);
5413 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5416 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1,
5418 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en);
5419 mutex_unlock(&rt5677->irq_lock);
5424 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5426 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask;
5431 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5433 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask;
5447 struct rt5677_priv *rt5677 = h->host_data;
5449 irq_set_chip_data(virq, rt5677);
5465 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5468 if (!rt5677->pdata.jd1_gpio &&
5469 !rt5677->pdata.jd2_gpio &&
5470 !rt5677->pdata.jd3_gpio)
5478 mutex_init(&rt5677->irq_lock);
5479 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check);
5486 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
5490 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff);
5493 if (rt5677->pdata.jd1_gpio) {
5495 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT;
5497 if (rt5677->pdata.jd2_gpio) {
5499 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT;
5501 if (rt5677->pdata.jd3_gpio) {
5503 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT;
5505 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val);
5508 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5512 rt5677->domain = irq_domain_create_linear(dev_fwnode(&i2c->dev),
5513 RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677);
5514 if (!rt5677->domain) {
5521 "rt5677", rt5677);
5525 rt5677->irq = i2c->irq;
5533 struct rt5677_priv *rt5677;
5537 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5539 if (rt5677 == NULL)
5542 rt5677->dev = &i2c->dev;
5543 rt5677->set_dsp_vad = rt5677_set_dsp_vad;
5544 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work);
5545 i2c_set_clientdata(i2c, rt5677);
5547 rt5677->type = (enum rt5677_type)(uintptr_t)device_get_match_data(dev);
5548 if (rt5677->type == 0)
5551 rt5677_read_device_properties(rt5677, &i2c->dev);
5557 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5559 if (IS_ERR(rt5677->pow_ldo2)) {
5560 ret = PTR_ERR(rt5677->pow_ldo2);
5564 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5566 if (IS_ERR(rt5677->reset_pin)) {
5567 ret = PTR_ERR(rt5677->reset_pin);
5572 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5580 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5582 if (IS_ERR(rt5677->regmap_physical)) {
5583 ret = PTR_ERR(rt5677->regmap_physical);
5589 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5590 if (IS_ERR(rt5677->regmap)) {
5591 ret = PTR_ERR(rt5677->regmap);
5597 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5600 "Device with ID register %#x is not rt5677\n", val);
5604 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5606 ret = regmap_register_patch(rt5677->regmap, init_list,
5611 if (rt5677->pdata.in1_diff)
5612 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5615 if (rt5677->pdata.in2_diff)
5616 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5619 if (rt5677->pdata.lout1_diff)
5620 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5623 if (rt5677->pdata.lout2_diff)
5624 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5627 if (rt5677->pdata.lout3_diff)
5628 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5631 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5632 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5635 rt5677_update_gpio_bits(rt5677, RT5677_GPIO5,
5640 if (rt5677->pdata.micbias1_vdd_3v3)
5641 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,