Lines Matching defs:nau8540
27 #include "nau8540.h"
237 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
242 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
244 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
247 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
249 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
259 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
262 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
263 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
361 nau8540_get_osr(struct nau8540 *nau8540)
365 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
376 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
379 osr = nau8540_get_osr(nau8540);
392 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
402 osr = nau8540_get_osr(nau8540);
407 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
428 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
437 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
481 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
484 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
486 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
508 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
521 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
524 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
526 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
546 .name = "nau8540-hifi",
667 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
673 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
679 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
686 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
693 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
696 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
702 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
705 dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
709 nau8540_fll_apply(nau8540->regmap, &fll_param);
711 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
720 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
725 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
727 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
732 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
734 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
739 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
743 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
755 static void nau8540_init_regs(struct nau8540 *nau8540)
757 struct regmap *regmap = nau8540->regmap;
794 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
796 regcache_cache_only(nau8540->regmap, true);
797 regcache_mark_dirty(nau8540->regmap);
804 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
806 regcache_cache_only(nau8540->regmap, false);
807 regcache_sync(nau8540->regmap);
846 struct nau8540 *nau8540 = dev_get_platdata(dev);
849 if (!nau8540) {
850 nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
851 if (!nau8540)
854 i2c_set_clientdata(i2c, nau8540);
856 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
857 if (IS_ERR(nau8540->regmap))
858 return PTR_ERR(nau8540->regmap);
859 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
866 nau8540->dev = dev;
867 nau8540_reset_chip(nau8540->regmap);
868 nau8540_init_regs(nau8540);
875 { "nau8540", 0 },
882 { .compatible = "nuvoton,nau8540", },
890 .name = "nau8540",