Lines Matching refs:wsa
19 #include "lpass-wsa-macro.h"
819 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
821 wsa->spkr_mode = mode;
855 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
857 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
907 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
909 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
1000 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1005 *tx_slot = wsa->active_ch_mask[dai->id];
1006 *tx_num = wsa->active_ch_cnt[dai->id];
1010 for_each_set_bit(temp, &wsa->active_ch_mask[dai->id],
1105 static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
1107 struct regmap *regmap = wsa->regmap;
1110 if (wsa->wsa_mclk_users == 0) {
1124 wsa->wsa_mclk_users++;
1126 if (wsa->wsa_mclk_users <= 0) {
1127 dev_err(wsa->dev, "clock already disabled\n");
1128 wsa->wsa_mclk_users = 0;
1131 wsa->wsa_mclk_users--;
1132 if (wsa->wsa_mclk_users == 0) {
1149 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1151 wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU);
1160 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1163 if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1166 } else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1297 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1299 if (!wsa->comp_enabled[comp])
1345 struct wsa_macro *wsa,
1355 if (wsa->softclip_clk_users[path] == 0) {
1364 wsa->softclip_clk_users[path]++;
1366 wsa->softclip_clk_users[path]--;
1367 if (wsa->softclip_clk_users[path] == 0) {
1383 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1391 if (!wsa->is_softclip_on[softclip_path])
1399 wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1410 wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1494 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1500 wsa->prim_int_users[ind]++;
1501 if (wsa->prim_int_users[ind] == 1) {
1522 wsa->prim_int_users[ind]--;
1523 if (wsa->prim_int_users[ind] == 0) {
1536 struct wsa_macro *wsa,
1541 switch (wsa->spkr_mode) {
1555 if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1557 (wsa->ear_spkr_gain != 0)) {
1559 val = comp_gain_offset + wsa->ear_spkr_gain - 1;
1568 if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1570 (wsa->ear_spkr_gain != 0)) {
1587 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1606 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1607 (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1608 wsa->comp_enabled[WSA_MACRO_COMP2])) {
1628 wsa_macro_config_ear_spkr_gain(component, wsa,
1635 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1636 (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1637 wsa->comp_enabled[WSA_MACRO_COMP2])) {
1655 wsa_macro_config_ear_spkr_gain(component, wsa,
1719 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1739 if (wsa->ec_hq[ec_tx]) {
1760 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1762 ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx];
1773 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1775 wsa->ec_hq[ec_tx] = value;
1786 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1788 ucontrol->value.integer.value[0] = wsa->comp_enabled[comp];
1798 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1800 wsa->comp_enabled[comp] = value;
1809 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1811 ucontrol->value.integer.value[0] = wsa->ear_spkr_gain;
1820 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1822 wsa->ear_spkr_gain = ucontrol->value.integer.value[0];
1834 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1837 wsa->rx_port_value[widget->shift];
1853 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1855 aif_rst = wsa->rx_port_value[widget->shift];
1864 wsa->rx_port_value[widget->shift] = rx_port_value;
1870 if (wsa->active_ch_cnt[aif_rst]) {
1872 &wsa->active_ch_mask[aif_rst]);
1873 wsa->active_ch_cnt[aif_rst]--;
1879 &wsa->active_ch_mask[rx_port_value]);
1880 wsa->active_ch_cnt[rx_port_value]++;
1898 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1901 ucontrol->value.integer.value[0] = wsa->is_softclip_on[path];
1910 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1913 wsa->is_softclip_on[path] = ucontrol->value.integer.value[0];
1972 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1976 if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id]))
1990 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1997 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1999 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2000 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
2004 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2006 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2007 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
2012 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2014 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2015 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
2019 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2021 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2022 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
2255 static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
2257 struct regmap *regmap = wsa->regmap;
2262 ret = clk_prepare_enable(wsa->mclk);
2264 dev_err(wsa->dev, "failed to enable mclk\n");
2267 wsa_macro_mclk_enable(wsa, true);
2276 wsa_macro_mclk_enable(wsa, false);
2277 clk_disable_unprepare(wsa->mclk);
2285 struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp);
2287 snd_soc_component_init_regmap(comp, wsa->regmap);
2289 wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB;
2317 struct wsa_macro *wsa = to_wsa_macro(hw);
2320 regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val);
2339 static int wsa_macro_register_mclk_output(struct wsa_macro *wsa)
2341 struct device *dev = wsa->dev;
2347 if (wsa->npl)
2348 parent_clk_name = __clk_get_name(wsa->npl);
2350 parent_clk_name = __clk_get_name(wsa->mclk);
2359 wsa->hw.init = &init;
2360 hw = &wsa->hw;
2361 ret = clk_hw_register(wsa->dev, hw);
2382 struct wsa_macro *wsa;
2389 wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL);
2390 if (!wsa)
2393 wsa->macro = devm_clk_get_optional(dev, "macro");
2394 if (IS_ERR(wsa->macro))
2395 return dev_err_probe(dev, PTR_ERR(wsa->macro), "unable to get macro clock\n");
2397 wsa->dcodec = devm_clk_get_optional(dev, "dcodec");
2398 if (IS_ERR(wsa->dcodec))
2399 return dev_err_probe(dev, PTR_ERR(wsa->dcodec), "unable to get dcodec clock\n");
2401 wsa->mclk = devm_clk_get(dev, "mclk");
2402 if (IS_ERR(wsa->mclk))
2403 return dev_err_probe(dev, PTR_ERR(wsa->mclk), "unable to get mclk clock\n");
2406 wsa->npl = devm_clk_get(dev, "npl");
2407 if (IS_ERR(wsa->npl))
2408 return dev_err_probe(dev, PTR_ERR(wsa->npl), "unable to get npl clock\n");
2411 wsa->fsgen = devm_clk_get(dev, "fsgen");
2412 if (IS_ERR(wsa->fsgen))
2413 return dev_err_probe(dev, PTR_ERR(wsa->fsgen), "unable to get fsgen clock\n");
2419 wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config);
2420 if (IS_ERR(wsa->regmap))
2421 return PTR_ERR(wsa->regmap);
2423 dev_set_drvdata(dev, wsa);
2425 wsa->dev = dev;
2428 clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ);
2429 clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ);
2431 ret = clk_prepare_enable(wsa->macro);
2435 ret = clk_prepare_enable(wsa->dcodec);
2439 ret = clk_prepare_enable(wsa->mclk);
2443 ret = clk_prepare_enable(wsa->npl);
2447 ret = clk_prepare_enable(wsa->fsgen);
2452 regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2455 regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2459 regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2474 ret = wsa_macro_register_mclk_output(wsa);
2481 clk_disable_unprepare(wsa->fsgen);
2483 clk_disable_unprepare(wsa->npl);
2485 clk_disable_unprepare(wsa->mclk);
2487 clk_disable_unprepare(wsa->dcodec);
2489 clk_disable_unprepare(wsa->macro);
2497 struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev);
2499 clk_disable_unprepare(wsa->macro);
2500 clk_disable_unprepare(wsa->dcodec);
2501 clk_disable_unprepare(wsa->mclk);
2502 clk_disable_unprepare(wsa->npl);
2503 clk_disable_unprepare(wsa->fsgen);
2508 struct wsa_macro *wsa = dev_get_drvdata(dev);
2510 regcache_cache_only(wsa->regmap, true);
2511 regcache_mark_dirty(wsa->regmap);
2513 clk_disable_unprepare(wsa->fsgen);
2514 clk_disable_unprepare(wsa->npl);
2515 clk_disable_unprepare(wsa->mclk);
2522 struct wsa_macro *wsa = dev_get_drvdata(dev);
2525 ret = clk_prepare_enable(wsa->mclk);
2531 ret = clk_prepare_enable(wsa->npl);
2537 ret = clk_prepare_enable(wsa->fsgen);
2543 regcache_cache_only(wsa->regmap, false);
2544 regcache_sync(wsa->regmap);
2548 clk_disable_unprepare(wsa->npl);
2550 clk_disable_unprepare(wsa->mclk);
2561 .compatible = "qcom,sc7280-lpass-wsa-macro",
2564 .compatible = "qcom,sm8250-lpass-wsa-macro",
2567 .compatible = "qcom,sm8450-lpass-wsa-macro",
2570 .compatible = "qcom,sm8550-lpass-wsa-macro",
2572 .compatible = "qcom,sc8280xp-lpass-wsa-macro",