Lines Matching refs:va
441 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable)
443 struct regmap *regmap = va->regmap;
474 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable)
476 struct regmap *regmap = va->regmap;
479 va_clk_rsc_fs_gen_request(va, true);
483 va_clk_rsc_fs_gen_request(va, false);
493 struct va_macro *va = snd_soc_component_get_drvdata(comp);
497 return clk_prepare_enable(va->fsgen);
499 clk_disable_unprepare(va->fsgen);
556 struct va_macro *va = snd_soc_component_get_drvdata(component);
558 if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
579 struct va_macro *va = snd_soc_component_get_drvdata(component);
582 set_bit(dec_id, &va->active_ch_mask[dai_id]);
583 va->active_ch_cnt[dai_id]++;
585 clear_bit(dec_id, &va->active_ch_mask[dai_id]);
586 va->active_ch_cnt[dai_id]--;
597 struct va_macro *va = snd_soc_component_get_drvdata(component);
607 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt);
608 dmic_clk_div = &(va->dmic_0_1_clk_div);
614 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt);
615 dmic_clk_div = &(va->dmic_2_3_clk_div);
621 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt);
622 dmic_clk_div = &(va->dmic_4_5_clk_div);
628 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt);
629 dmic_clk_div = &(va->dmic_6_7_clk_div);
640 clk_div = va->dmic_clk_div;
681 clk_div = va->dmic_clk_div;
683 clk_div = va->dmic_clk_div;
732 struct va_macro *va = snd_soc_component_get_drvdata(comp);
749 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT);
812 struct va_macro *va = snd_soc_component_get_drvdata(comp);
816 ucontrol->value.enumerated.item[0] = va->dec_mode[path];
828 struct va_macro *va = snd_soc_component_get_drvdata(comp);
830 va->dec_mode[path] = value;
844 struct va_macro *va = snd_soc_component_get_drvdata(component);
875 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
891 struct va_macro *va = snd_soc_component_get_drvdata(component);
897 *tx_slot = va->active_ch_mask[dai->id];
898 *tx_num = va->active_ch_cnt[dai->id];
910 struct va_macro *va = snd_soc_component_get_drvdata(component);
913 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
1311 struct va_macro *va = snd_soc_component_get_drvdata(component);
1313 snd_soc_component_init_regmap(component, va->regmap);
1331 struct va_macro *va = to_va_macro(hw);
1332 struct regmap *regmap = va->regmap;
1335 ret = va_macro_mclk_enable(va, true);
1336 if (va->has_swr_master)
1345 struct va_macro *va = to_va_macro(hw);
1346 struct regmap *regmap = va->regmap;
1348 if (va->has_swr_master)
1352 va_macro_mclk_enable(va, false);
1357 struct va_macro *va = to_va_macro(hw);
1360 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val);
1371 static int va_macro_register_fsgen_output(struct va_macro *va)
1373 struct clk *parent = va->mclk;
1374 struct device *dev = va->dev;
1390 va->hw.init = &init;
1391 ret = devm_clk_hw_register(va->dev, &va->hw);
1395 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw);
1399 struct va_macro *va)
1411 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1414 va->dmic_clk_div = VA_MACRO_CLK_DIV_3;
1417 va->dmic_clk_div = VA_MACRO_CLK_DIV_4;
1420 va->dmic_clk_div = VA_MACRO_CLK_DIV_6;
1423 va->dmic_clk_div = VA_MACRO_CLK_DIV_8;
1426 va->dmic_clk_div = VA_MACRO_CLK_DIV_16;
1436 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n",
1447 struct va_macro *va;
1452 va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL);
1453 if (!va)
1456 va->dev = dev;
1458 va->macro = devm_clk_get_optional(dev, "macro");
1459 if (IS_ERR(va->macro))
1460 return dev_err_probe(dev, PTR_ERR(va->macro), "unable to get macro clock\n");
1462 va->dcodec = devm_clk_get_optional(dev, "dcodec");
1463 if (IS_ERR(va->dcodec))
1464 return dev_err_probe(dev, PTR_ERR(va->dcodec), "unable to get dcodec clock\n");
1466 va->mclk = devm_clk_get(dev, "mclk");
1467 if (IS_ERR(va->mclk))
1468 return dev_err_probe(dev, PTR_ERR(va->mclk), "unable to get mclk clock\n");
1470 va->pds = lpass_macro_pds_init(dev);
1471 if (IS_ERR(va->pds))
1472 return PTR_ERR(va->pds);
1478 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1480 ret = va_macro_validate_dmic_sample_rate(sample_rate, va);
1493 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config);
1494 if (IS_ERR(va->regmap)) {
1499 dev_set_drvdata(dev, va);
1502 va->has_swr_master = data->has_swr_master;
1505 clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);
1507 ret = clk_prepare_enable(va->macro);
1511 ret = clk_prepare_enable(va->dcodec);
1515 ret = clk_prepare_enable(va->mclk);
1519 if (va->has_swr_master) {
1521 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0,
1524 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL1,
1527 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL2,
1533 if (va->has_swr_master) {
1534 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1536 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1538 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1554 ret = va_macro_register_fsgen_output(va);
1558 va->fsgen = clk_hw_get_clk(&va->hw, "fsgen");
1559 if (IS_ERR(va->fsgen)) {
1560 ret = PTR_ERR(va->fsgen);
1567 clk_disable_unprepare(va->mclk);
1569 clk_disable_unprepare(va->dcodec);
1571 clk_disable_unprepare(va->macro);
1573 lpass_macro_pds_exit(va->pds);
1580 struct va_macro *va = dev_get_drvdata(&pdev->dev);
1582 clk_disable_unprepare(va->mclk);
1583 clk_disable_unprepare(va->dcodec);
1584 clk_disable_unprepare(va->macro);
1586 lpass_macro_pds_exit(va->pds);
1591 struct va_macro *va = dev_get_drvdata(dev);
1593 regcache_cache_only(va->regmap, true);
1594 regcache_mark_dirty(va->regmap);
1596 clk_disable_unprepare(va->mclk);
1603 struct va_macro *va = dev_get_drvdata(dev);
1606 ret = clk_prepare_enable(va->mclk);
1608 dev_err(va->dev, "unable to prepare mclk\n");
1612 regcache_cache_only(va->regmap, false);
1613 regcache_sync(va->regmap);
1624 { .compatible = "qcom,sc7280-lpass-va-macro", .data = &sm8250_va_data },
1625 { .compatible = "qcom,sm8250-lpass-va-macro", .data = &sm8250_va_data },
1626 { .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data },
1627 { .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data },