Lines Matching defs:cs43130
3 * cs43130.c -- CS43130 ALSA Soc Audio driver
38 #include "cs43130.h"
239 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
242 dev_dbg(component->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n",
243 cs43130->mclk, cs43130->mclk_int);
245 pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int);
250 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
253 cs43130->pll_bypass = true;
257 cs43130->pll_bypass = false;
259 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2,
263 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3,
267 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4,
271 regmap_write(cs43130->regmap, CS43130_PLL_SET_5,
273 regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout);
274 regmap_write(cs43130->regmap, CS43130_PLL_SET_7,
276 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8,
279 regmap_write(cs43130->regmap, CS43130_PLL_SET_9,
281 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
291 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
304 cs43130->mclk = freq_in;
314 cs43130->mclk_int = freq_out;
317 cs43130->mclk_int = freq_out;
326 dev_dbg(component->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass);
334 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
337 if (src == cs43130->mclk_int_src) {
342 switch (cs43130->mclk_int) {
350 dev_err(component->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int);
356 cs43130->pll_bypass = true;
357 cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT;
358 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
359 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
363 reinit_completion(&cs43130->xtal_rdy);
364 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
366 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
368 ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
370 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
379 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
382 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
387 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
392 cs43130->pll_bypass = false;
393 cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL;
394 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
395 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
399 reinit_completion(&cs43130->xtal_rdy);
400 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
402 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
404 ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
406 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
415 reinit_completion(&cs43130->pll_rdy);
416 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
418 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
420 ret = wait_for_completion_timeout(&cs43130->pll_rdy,
422 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
430 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
433 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
439 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
441 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
444 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
449 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
452 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
559 struct cs43130_private *cs43130)
574 switch (cs43130->dais[dai_id].dai_format) {
599 switch (cs43130->dais[dai_id].dai_mode) {
632 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,
635 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,
638 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,
641 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,
644 regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data);
645 regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1);
646 regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2);
647 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,
649 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,
651 regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data);
654 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1,
657 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2,
660 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1,
663 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2,
666 regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data);
667 regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1);
668 regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2);
669 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN,
671 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN,
673 regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data);
681 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
687 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
693 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
699 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
714 regmap_write(cs43130->regmap, CS43130_ASP_DEN_1,
717 regmap_write(cs43130->regmap, CS43130_ASP_DEN_2,
720 regmap_write(cs43130->regmap, CS43130_ASP_NUM_1,
723 regmap_write(cs43130->regmap, CS43130_ASP_NUM_2,
728 regmap_write(cs43130->regmap, CS43130_XSP_DEN_1,
731 regmap_write(cs43130->regmap, CS43130_XSP_DEN_2,
734 regmap_write(cs43130->regmap, CS43130_XSP_NUM_1,
737 regmap_write(cs43130->regmap, CS43130_XSP_NUM_2,
776 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
780 mutex_lock(&cs43130->clk_mutex);
781 if (!cs43130->clk_req) {
788 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
789 if (cs43130->pll_bypass)
795 cs43130->clk_req++;
796 if (cs43130->clk_req == 2)
797 cs43130_pcm_dsd_mix(true, cs43130->regmap);
798 mutex_unlock(&cs43130->clk_mutex);
813 if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
814 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
817 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
820 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
823 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
835 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
837 unsigned int sclk = cs43130->dais[dai->id].sclk;
843 mutex_lock(&cs43130->clk_mutex);
844 if (!cs43130->clk_req) {
851 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
852 if (cs43130->pll_bypass)
858 cs43130->clk_req++;
859 if (cs43130->clk_req == 2)
860 cs43130_pcm_dsd_mix(true, cs43130->regmap);
861 mutex_unlock(&cs43130->clk_mutex);
884 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
893 regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val);
902 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
907 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
913 if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
938 cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap);
939 cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130);
948 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
950 mutex_lock(&cs43130->clk_mutex);
951 cs43130->clk_req--;
952 if (!cs43130->clk_req) {
955 cs43130_pcm_dsd_mix(false, cs43130->regmap);
957 mutex_unlock(&cs43130->clk_mutex);
1025 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1032 switch (cs43130->dev_id) {
1036 regmap_multi_reg_write(cs43130->regmap, pcm_ch_en_seq,
1039 regmap_multi_reg_write(cs43130->regmap, pcm_ch_dis_seq,
1146 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1150 switch (cs43130->dev_id) {
1153 regmap_multi_reg_write(cs43130->regmap, dsd_seq,
1159 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_1,
1161 switch (cs43130->dev_id) {
1164 regmap_multi_reg_write(cs43130->regmap, unmute_seq,
1170 switch (cs43130->dev_id) {
1173 regmap_multi_reg_write(cs43130->regmap, mute_seq,
1175 regmap_update_bits(cs43130->regmap,
1186 regmap_update_bits(cs43130->regmap,
1203 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1207 switch (cs43130->dev_id) {
1210 regmap_multi_reg_write(cs43130->regmap, pcm_seq,
1216 regmap_update_bits(cs43130->regmap, CS43130_PCM_PATH_CTL_1,
1218 switch (cs43130->dev_id) {
1221 regmap_multi_reg_write(cs43130->regmap, unmute_seq,
1227 switch (cs43130->dev_id) {
1230 regmap_multi_reg_write(cs43130->regmap, mute_seq,
1232 regmap_update_bits(cs43130->regmap,
1243 regmap_update_bits(cs43130->regmap,
1272 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1276 switch (cs43130->dev_id) {
1279 regmap_multi_reg_write(cs43130->regmap, pop_free_seq,
1284 regmap_multi_reg_write(cs43130->regmap, pop_free_seq2,
1292 regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
1294 switch (cs43130->dev_id) {
1297 regmap_multi_reg_write(cs43130->regmap, dac_postpmu_seq,
1305 regmap_write(cs43130->regmap, CS43130_DXD12, 0);
1310 regmap_write(cs43130->regmap, CS43130_DXD13, 0);
1314 regmap_write(cs43130->regmap, CS43130_DXD1, 0);
1317 switch (cs43130->dev_id) {
1320 regmap_multi_reg_write(cs43130->regmap, dac_postpmd_seq,
1352 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1356 regmap_multi_reg_write(cs43130->regmap, hpin_prepmd_seq,
1360 regmap_multi_reg_write(cs43130->regmap, hpin_postpmu_seq,
1473 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1477 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
1480 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
1489 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S;
1492 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J;
1495 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A;
1498 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B;
1508 cs43130->dais[codec_dai->id].dai_mode,
1509 cs43130->dais[codec_dai->id].dai_format);
1517 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1521 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
1524 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
1532 cs43130->dais[codec_dai->id].dai_mode);
1541 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1543 cs43130->dais[codec_dai->id].sclk = freq;
1545 cs43130->dais[codec_dai->id].sclk);
1575 .name = "cs43130-asp-pcm",
1588 .name = "cs43130-asp-dop",
1601 .name = "cs43130-xsp-dop",
1614 .name = "cs43130-xsp-dsd",
1632 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1640 cs43130->mclk = freq;
1648 cs43130->pll_bypass = true;
1666 struct cs43130_private *cs43130 = i2c_get_clientdata(client);
1668 if (!cs43130->hpload_done)
1671 return sysfs_emit(buf, "%u\n", cs43130->hpload_dc[ch]);
1703 struct cs43130_private *cs43130 = i2c_get_clientdata(client);
1705 if (cs43130->hpload_done && cs43130->ac_meas) {
1708 cs43130->hpload_ac[i][ch]);
1931 struct cs43130_private *cs43130)
1937 struct snd_soc_component *component = cs43130->component;
1947 regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, ®);
1956 regmap_read(cs43130->regmap, addr, ®);
1958 regmap_read(cs43130->regmap, addr + 1, ®);
1963 cs43130->hpload_dc[HP_LEFT] = impedance;
1965 cs43130->hpload_dc[HP_RIGHT] = impedance;
1971 cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance;
1973 cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance;
1976 cs43130->ac_freq[ac_idx], !left_ch, impedance);
1982 static int cs43130_hpload_proc(struct cs43130_private *cs43130,
1989 struct snd_soc_component *component = cs43130->component;
1991 reinit_completion(&cs43130->hpload_evt);
1994 ac_reg_val = cs43130_get_ac_reg_val(cs43130->ac_freq[ac_idx]);
1995 regmap_update_bits(cs43130->regmap, CS43130_HP_LOAD_1,
1997 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_1,
2000 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_2,
2005 regmap_multi_reg_write(cs43130->regmap, seq,
2008 ret = wait_for_completion_timeout(&cs43130->hpload_evt,
2010 regmap_read(cs43130->regmap, CS43130_INT_MASK_4, &msk);
2017 cs43130->hpload_stat, msk);
2018 if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT |
2021 !(cs43130->hpload_stat & rslt_msk)) {
2063 struct cs43130_private *cs43130;
2067 cs43130 = container_of(wk, struct cs43130_private, work);
2068 component = cs43130->component;
2070 if (!cs43130->mclk)
2073 cs43130->hpload_done = false;
2075 mutex_lock(&cs43130->clk_mutex);
2076 if (!cs43130->clk_req) {
2078 cs43130_set_pll(component, 0, 0, cs43130->mclk, CS43130_MCLK_22M);
2079 if (cs43130->pll_bypass)
2085 cs43130->clk_req++;
2086 mutex_unlock(&cs43130->clk_mutex);
2088 regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, ®);
2090 switch (cs43130->dev_id) {
2100 WARN(1, "Invalid dev_id for meas: %d", cs43130->dev_id);
2107 ret = cs43130_hpload_proc(cs43130, hpload_seq[i].seq,
2113 cs43130_update_hpload(hpload_seq[i].msk, ac_idx, cs43130);
2115 if (cs43130->ac_meas &&
2124 cs43130->hpload_done = true;
2126 if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD)
2127 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_LINEOUT,
2130 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_HEADPHONE,
2136 cs43130->dc_threshold[i]);
2138 cs43130_set_hv(cs43130->regmap, cs43130->hpload_dc[HP_LEFT],
2139 cs43130->dc_threshold);
2142 switch (cs43130->dev_id) {
2144 cs43130_hpload_proc(cs43130, hp_dis_cal_seq,
2149 cs43130_hpload_proc(cs43130, hp_dis_cal_seq2,
2155 regmap_multi_reg_write(cs43130->regmap, hp_cln_seq,
2158 mutex_lock(&cs43130->clk_mutex);
2159 cs43130->clk_req--;
2161 if (!cs43130->clk_req)
2163 mutex_unlock(&cs43130->clk_mutex);
2168 struct cs43130_private *cs43130 = (struct cs43130_private *)data;
2169 struct snd_soc_component *component = cs43130->component;
2176 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1 + i,
2178 regmap_read(cs43130->regmap, CS43130_INT_MASK_1 + i,
2194 complete(&cs43130->xtal_rdy);
2199 complete(&cs43130->pll_rdy);
2204 cs43130->hpload_stat = stickies[3];
2207 cs43130->hpload_stat);
2208 complete(&cs43130->hpload_evt);
2213 cs43130->hpload_stat = stickies[3];
2215 cs43130->hpload_stat);
2216 complete(&cs43130->hpload_evt);
2221 cs43130->hpload_stat = stickies[3];
2223 cs43130->hpload_stat);
2224 complete(&cs43130->hpload_evt);
2229 cs43130->hpload_stat = stickies[3];
2231 cs43130->hpload_stat);
2232 complete(&cs43130->hpload_evt);
2237 cs43130->hpload_stat = stickies[3];
2239 cs43130->hpload_stat);
2240 complete(&cs43130->hpload_evt);
2245 cs43130->hpload_stat = stickies[3];
2247 cs43130->hpload_stat);
2248 complete(&cs43130->hpload_evt);
2253 cs43130->hpload_stat = stickies[3];
2255 cs43130->hpload_stat);
2256 complete(&cs43130->hpload_evt);
2267 cs43130->hpload_done = false;
2268 snd_soc_jack_report(&cs43130->jack, 0, CS43130_JACK_MASK);
2273 if (cs43130->dc_meas && !cs43130->hpload_done &&
2274 !work_busy(&cs43130->work)) {
2276 queue_work(cs43130->wq, &cs43130->work);
2279 snd_soc_jack_report(&cs43130->jack, SND_JACK_MECHANICAL,
2290 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
2294 cs43130->component = component;
2296 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) {
2297 regmap_update_bits(cs43130->regmap, CS43130_CRYSTAL_SET,
2299 cs43130->xtal_ibias);
2300 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2305 &cs43130->jack);
2311 cs43130->hpload_done = false;
2312 if (cs43130->dc_meas) {
2317 cs43130->wq = create_singlethread_workqueue("cs43130_hp");
2318 if (!cs43130->wq) {
2322 INIT_WORK(&cs43130->work, cs43130_imp_meas);
2325 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, ®);
2326 regmap_read(cs43130->regmap, CS43130_HP_STATUS, ®);
2327 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2329 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
2331 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
2372 struct cs43130_private *cs43130)
2380 cs43130->xtal_ibias = CS43130_XTAL_UNUSED;
2386 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA;
2389 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA;
2392 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA;
2400 cs43130->dc_meas = of_property_read_bool(np, "cirrus,dc-measure");
2401 cs43130->ac_meas = of_property_read_bool(np, "cirrus,ac-measure");
2403 if (of_property_read_u16_array(np, "cirrus,ac-freq", cs43130->ac_freq,
2406 cs43130->ac_freq[i] = cs43130_ac_freq[i];
2410 cs43130->dc_threshold,
2413 cs43130->dc_threshold[i] = cs43130_dc_threshold[i];
2421 struct cs43130_private *cs43130;
2426 cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL);
2427 if (!cs43130)
2430 i2c_set_clientdata(client, cs43130);
2432 cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap);
2433 if (IS_ERR(cs43130->regmap)) {
2434 ret = PTR_ERR(cs43130->regmap);
2439 ret = cs43130_handle_device_data(client, cs43130);
2443 for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++)
2444 cs43130->supplies[i].supply = cs43130_supply_names[i];
2447 ARRAY_SIZE(cs43130->supplies),
2448 cs43130->supplies);
2453 ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies),
2454 cs43130->supplies);
2460 cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev,
2462 if (IS_ERR(cs43130->reset_gpio)) {
2463 ret = PTR_ERR(cs43130->reset_gpio);
2467 gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
2471 devid = cirrus_read_device_id(cs43130->regmap, CS43130_DEVID_AB);
2493 cs43130->dev_id = devid;
2494 ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®);
2504 mutex_init(&cs43130->clk_mutex);
2506 init_completion(&cs43130->xtal_rdy);
2507 init_completion(&cs43130->pll_rdy);
2508 init_completion(&cs43130->hpload_evt);
2513 "cs43130", cs43130);
2519 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
2526 switch (cs43130->dev_id) {
2569 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
2571 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
2577 gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
2579 regulator_bulk_disable(ARRAY_SIZE(cs43130->supplies),
2580 cs43130->supplies);
2587 struct cs43130_private *cs43130 = i2c_get_clientdata(client);
2589 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
2590 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2594 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2598 if (cs43130->dc_meas) {
2599 cancel_work_sync(&cs43130->work);
2600 flush_workqueue(cs43130->wq);
2608 gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
2611 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2616 struct cs43130_private *cs43130 = dev_get_drvdata(dev);
2618 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
2619 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2623 regcache_cache_only(cs43130->regmap, true);
2624 regcache_mark_dirty(cs43130->regmap);
2626 gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
2628 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2635 struct cs43130_private *cs43130 = dev_get_drvdata(dev);
2638 ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2644 regcache_cache_only(cs43130->regmap, false);
2646 gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
2650 ret = regcache_sync(cs43130->regmap);
2656 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
2657 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2662 regcache_cache_only(cs43130->regmap, true);
2663 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2674 {.compatible = "cirrus,cs43130",},
2684 {"cs43130", 0},
2695 .name = "cs43130",