Lines Matching refs:base
169 pm_runtime_get_noresume(cs35l56->base.dev);
171 regcache_cache_only(cs35l56->base.regmap, false);
175 regcache_cache_only(cs35l56->base.regmap, true);
183 if (cs35l56->base.init_done) {
190 pm_runtime_mark_last_busy(cs35l56->base.dev);
191 pm_runtime_put_autosuspend(cs35l56->base.dev);
201 dev_dbg(cs35l56->base.dev, "int control_port=%#x\n", status->control_port);
210 pm_runtime_get_noresume(cs35l56->base.dev);
233 cs35l56_irq(-1, &cs35l56->base);
240 pm_runtime_put_autosuspend(cs35l56->base.dev);
249 ports = devm_kcalloc(cs35l56->base.dev, 2, sizeof(*ports), GFP_KERNEL);
282 dev_dbg(cs35l56->base.dev, "%s: ATTACHED\n", __func__);
286 if (!cs35l56->base.init_done || cs35l56->soft_resetting)
292 dev_dbg(cs35l56->base.dev, "%s: UNATTACHED\n", __func__);
308 if (!cs35l56->base.init_done)
327 dev_err(cs35l56->base.dev, "Failed to read current clock scale: %d\n", curr_scale);
333 dev_err(cs35l56->base.dev, "Failed to read next clock scale: %d\n", next_scale);
341 dev_err(cs35l56->base.dev, "Failed to modify current clock scale: %d\n",
350 dev_err(cs35l56->base.dev, "Failed to modify current clock scale: %d\n", ret);
354 dev_dbg(cs35l56->base.dev, "Next bus scale: %#x\n", next_scale);
366 dev_dbg(cs35l56->base.dev, "%s: sclk=%u c=%u r=%u\n",
369 if (cs35l56->base.rev < 0xb0)
381 dev_dbg(cs35l56->base.dev, "%s: mode:%d type:%d\n", __func__, mode, type);
402 dev_dbg(cs35l56->base.dev, "Wait for initialization_complete\n");
405 dev_err(cs35l56->base.dev, "initialization_complete timed out\n");
424 if (!cs35l56->base.init_done)
427 return cs35l56_runtime_suspend_common(&cs35l56->base);
437 if (!cs35l56->base.init_done)
444 ret = cs35l56_runtime_resume_common(&cs35l56->base, true);
459 if (!cs35l56->base.init_done)
498 cs35l56->base.dev = dev;
504 cs35l56->base.regmap = devm_regmap_init(dev, &cs35l56_regmap_bus_sdw,
506 if (IS_ERR(cs35l56->base.regmap)) {
507 ret = PTR_ERR(cs35l56->base.regmap);
512 regcache_cache_only(cs35l56->base.regmap, true);