Lines Matching refs:cs35l45
3 // cs35l45.c - CS35L45 ALSA SoC audio driver
21 #include "cs35l45.h"
46 static int cs35l45_set_cspl_mbox_cmd(struct cs35l45_private *cs35l45,
53 if (!cs35l45->dsp.cs_dsp.running) {
54 dev_err(cs35l45->dev, "DSP not running\n");
62 dev_err(cs35l45->dev, "Failed to write MBOX: %d\n", ret);
72 dev_err(cs35l45->dev, "Failed to read MBOX STS: %d\n", ret);
77 dev_dbg(cs35l45->dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts);
83 dev_err(cs35l45->dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts);
92 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
94 dev_dbg(cs35l45->dev, "%s event : %x\n", __func__, event);
98 regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES,
106 regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, 0);
119 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
124 if (cs35l45->dsp.cs_dsp.booted)
129 if (cs35l45->dsp.cs_dsp.running)
132 regmap_set_bits(cs35l45->regmap, CS35L45_PWRMGT_CTL,
137 if (cs35l45->dsp.preloaded)
140 if (cs35l45->dsp.cs_dsp.running) {
156 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
160 return cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap,
163 return cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap,
449 static int cs35l45_set_pll(struct cs35l45_private *cs35l45, unsigned int freq)
456 dev_err(cs35l45->dev, "Invalid freq: %u\n", freq);
460 regmap_read(cs35l45->regmap, CS35L45_REFCLK_INPUT, &val);
465 regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK);
466 regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT,
469 regmap_clear_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK);
470 regmap_clear_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK);
471 regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK);
478 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(codec_dai->component);
485 dev_err(cs35l45->dev, "Invalid DAI clocking\n");
497 dev_err(cs35l45->dev, "Invalid DAI format\n");
519 dev_warn(cs35l45->dev, "Invalid DAI clock polarity\n");
523 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2,
538 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
556 dev_warn(cs35l45->dev, "Unsupported sample rate (%d)\n",
561 regmap_update_bits(cs35l45->regmap, CS35L45_GLOBAL_SAMPLE_RATE,
567 if (cs35l45->slot_width)
568 asp_width = cs35l45->slot_width;
573 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2,
577 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL5,
581 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2,
585 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL1,
590 if (cs35l45->sysclk_set)
594 regmap_read(cs35l45->regmap, CS35L45_ASP_CONTROL2, &asp_fmt);
602 cs35l45->slot_count, slot_multiple);
604 return cs35l45_set_pll(cs35l45, bclk);
611 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
616 cs35l45->slot_width = slot_width;
617 cs35l45->slot_count = slots;
625 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
629 dev_err(cs35l45->dev, "Invalid clk_id %d\n", clk_id);
633 cs35l45->sysclk_set = false;
637 ret = cs35l45_set_pll(cs35l45, freq);
641 cs35l45->sysclk_set = true;
648 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
654 regmap_read(cs35l45->regmap, CS35L45_GLOBAL_SAMPLE_RATE, &global_fs);
668 regmap_read(cs35l45->regmap, CS35L45_AMP_PCM_HPF_TST, &val);
679 regmap_multi_reg_write(cs35l45->regmap, hpf_override_seq,
696 .name = "cs35l45",
719 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
721 return wm_adsp2_component_probe(&cs35l45->dsp, component);
726 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
728 wm_adsp2_component_remove(&cs35l45->dsp, component);
744 .name = "cs35l45",
749 static void cs35l45_setup_hibernate(struct cs35l45_private *cs35l45)
753 if (cs35l45->bus_type == CONTROL_BUS_I2C)
758 regmap_update_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL,
762 regmap_set_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL,
765 regmap_update_bits(cs35l45->regmap, CS35L45_WKI2C_CTL,
766 CS35L45_WKI2C_ADDR_MASK, cs35l45->i2c_addr);
768 regmap_set_bits(cs35l45->regmap, CS35L45_WKI2C_CTL,
772 static int cs35l45_enter_hibernate(struct cs35l45_private *cs35l45)
774 dev_dbg(cs35l45->dev, "Enter hibernate\n");
776 cs35l45_setup_hibernate(cs35l45);
778 regmap_set_bits(cs35l45->regmap, CS35L45_IRQ1_MASK_2, CS35L45_DSP_VIRT2_MBOX_MASK);
781 regmap_write(cs35l45->regmap, CS35L45_DSP_VIRT1_MBOX_1, CSPL_MBOX_CMD_HIBERNATE);
786 static int cs35l45_exit_hibernate(struct cs35l45_private *cs35l45)
793 dev_dbg(cs35l45->dev, "Exit hibernate\n");
796 ret = cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap,
799 dev_dbg(cs35l45->dev, "Wake success at cycle: %d\n", j);
800 regmap_clear_bits(cs35l45->regmap, CS35L45_IRQ1_MASK_2,
807 dev_err(cs35l45->dev, "Wake failed, re-enter hibernate: %d\n", ret);
809 cs35l45_setup_hibernate(cs35l45);
812 dev_err(cs35l45->dev, "Timed out waking device\n");
819 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
821 if (!cs35l45->dsp.preloaded || !cs35l45->dsp.cs_dsp.running)
824 cs35l45_enter_hibernate(cs35l45);
826 regcache_cache_only(cs35l45->regmap, true);
827 regcache_mark_dirty(cs35l45->regmap);
829 dev_dbg(cs35l45->dev, "Runtime suspended\n");
836 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
839 if (!cs35l45->dsp.preloaded || !cs35l45->dsp.cs_dsp.running)
842 dev_dbg(cs35l45->dev, "Runtime resume\n");
844 regcache_cache_only(cs35l45->regmap, false);
846 ret = cs35l45_exit_hibernate(cs35l45);
850 ret = regcache_sync(cs35l45->regmap);
852 dev_warn(cs35l45->dev, "regcache_sync failed: %d\n", ret);
855 regmap_clear_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);
856 regmap_set_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);
857 regmap_clear_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);
863 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
865 dev_dbg(cs35l45->dev, "System suspend, disabling IRQ\n");
866 disable_irq(cs35l45->irq);
873 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
875 dev_dbg(cs35l45->dev, "Late system suspend, reenabling IRQ\n");
876 enable_irq(cs35l45->irq);
883 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
885 dev_dbg(cs35l45->dev, "Early system resume, disabling IRQ\n");
886 disable_irq(cs35l45->irq);
893 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
895 dev_dbg(cs35l45->dev, "System resume, reenabling IRQ\n");
896 enable_irq(cs35l45->irq);
901 static int cs35l45_apply_property_config(struct cs35l45_private *cs35l45)
903 struct device_node *node = cs35l45->dev->of_node;
924 regmap_update_bits(cs35l45->regmap, gpio_regs[i],
930 regmap_update_bits(cs35l45->regmap, gpio_regs[i],
936 regmap_update_bits(cs35l45->regmap, gpio_regs[i],
942 regmap_update_bits(cs35l45->regmap, gpio_regs[i],
948 regmap_update_bits(cs35l45->regmap, pad_regs[i],
954 regmap_update_bits(cs35l45->regmap, pad_regs[i],
958 cs35l45->irq_invert = val;
964 if (device_property_read_u32(cs35l45->dev,
966 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL3,
974 static int cs35l45_dsp_virt2_mbox3_irq_handle(struct cs35l45_private *cs35l45,
994 dev_info(cs35l45->dev, "MBOX event (SPEAKER_STATUS): %s\n",
998 dev_dbg(cs35l45->dev, "MBOX event (BOOT_DONE)\n");
1001 dev_err(cs35l45->dev, "MBOX event not supported %u\n", cmd);
1010 struct cs35l45_private *cs35l45 = data;
1014 ret = regmap_read(cs35l45->regmap, CS35L45_DSP_VIRT2_MBOX_3, &mbox_val);
1016 cs35l45_dsp_virt2_mbox3_irq_handle(cs35l45, mbox_val & CS35L45_MBOX3_CMD_MASK,
1020 ret = regmap_read(cs35l45->regmap, CS35L45_DSP_VIRT2_MBOX_4, &mbox_val);
1022 dev_err(cs35l45->dev, "Spurious DSP MBOX4 IRQ\n");
1030 struct cs35l45_private *cs35l45 = data;
1032 dev_dbg(cs35l45->dev, "PLL unlock detected!");
1039 struct cs35l45_private *cs35l45 = data;
1041 dev_dbg(cs35l45->dev, "PLL lock detected!");
1065 struct cs35l45_private *cs35l45 = data;
1068 i = irq - regmap_irq_get_virq(cs35l45->irq_data, 0);
1070 dev_err(cs35l45->dev, "%s condition detected!\n", cs35l45_irqs[i].name);
1091 .name = "cs35l45 IRQ1 Controller",
1102 static int cs35l45_initialize(struct cs35l45_private *cs35l45)
1104 struct device *dev = cs35l45->dev;
1109 ret = regmap_read_poll_timeout(cs35l45->regmap, CS35L45_IRQ1_EINT_4, sts,
1113 dev_err(cs35l45->dev, "Timeout waiting for OTP boot\n");
1117 ret = regmap_bulk_read(cs35l45->regmap, CS35L45_DEVID, dev_id, ARRAY_SIZE(dev_id));
1119 dev_err(cs35l45->dev, "Get Device ID failed: %d\n", ret);
1128 dev_err(cs35l45->dev, "Bad DEVID 0x%x\n", dev_id[0]);
1132 dev_info(cs35l45->dev, "Cirrus Logic CS35L45: REVID %02X OTPID %02X\n",
1135 regmap_write(cs35l45->regmap, CS35L45_IRQ1_EINT_4,
1138 ret = cs35l45_apply_patch(cs35l45);
1144 ret = cs35l45_apply_property_config(cs35l45);
1178 static int cs35l45_dsp_init(struct cs35l45_private *cs35l45)
1180 struct wm_adsp *dsp = &cs35l45->dsp;
1183 dsp->part = "cs35l45";
1189 dsp->cs_dsp.dev = cs35l45->dev;
1190 dsp->cs_dsp.regmap = cs35l45->regmap;
1199 regmap_multi_reg_write(cs35l45->regmap, cs35l45_fs_errata_patch,
1205 int cs35l45_probe(struct cs35l45_private *cs35l45)
1207 struct device *dev = cs35l45->dev;
1211 cs35l45->vdd_batt = devm_regulator_get(dev, "vdd-batt");
1212 if (IS_ERR(cs35l45->vdd_batt))
1213 return dev_err_probe(dev, PTR_ERR(cs35l45->vdd_batt),
1216 cs35l45->vdd_a = devm_regulator_get(dev, "vdd-a");
1217 if (IS_ERR(cs35l45->vdd_a))
1218 return dev_err_probe(dev, PTR_ERR(cs35l45->vdd_a),
1222 ret = regulator_enable(cs35l45->vdd_batt);
1226 ret = regulator_enable(cs35l45->vdd_a);
1231 cs35l45->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1232 if (IS_ERR(cs35l45->reset_gpio)) {
1233 ret = PTR_ERR(cs35l45->reset_gpio);
1234 cs35l45->reset_gpio = NULL;
1243 if (cs35l45->reset_gpio) {
1245 gpiod_set_value_cansleep(cs35l45->reset_gpio, 1);
1250 ret = cs35l45_initialize(cs35l45);
1254 ret = cs35l45_dsp_init(cs35l45);
1258 pm_runtime_set_autosuspend_delay(cs35l45->dev, 3000);
1259 pm_runtime_use_autosuspend(cs35l45->dev);
1260 pm_runtime_mark_last_busy(cs35l45->dev);
1261 pm_runtime_set_active(cs35l45->dev);
1262 pm_runtime_get_noresume(cs35l45->dev);
1263 pm_runtime_enable(cs35l45->dev);
1265 if (cs35l45->irq) {
1266 if (cs35l45->irq_invert)
1271 ret = devm_regmap_add_irq_chip(dev, cs35l45->regmap, cs35l45->irq, irq_pol, 0,
1272 &cs35l45_regmap_irq_chip, &cs35l45->irq_data);
1279 irq = regmap_irq_get_virq(cs35l45->irq_data, cs35l45_irqs[i].irq);
1287 irq_pol, cs35l45_irqs[i].name, cs35l45);
1302 pm_runtime_put_autosuspend(cs35l45->dev);
1307 pm_runtime_disable(cs35l45->dev);
1308 pm_runtime_put_noidle(cs35l45->dev);
1309 wm_adsp2_remove(&cs35l45->dsp);
1312 gpiod_set_value_cansleep(cs35l45->reset_gpio, 0);
1314 regulator_disable(cs35l45->vdd_a);
1315 regulator_disable(cs35l45->vdd_batt);
1321 void cs35l45_remove(struct cs35l45_private *cs35l45)
1323 pm_runtime_get_sync(cs35l45->dev);
1324 pm_runtime_disable(cs35l45->dev);
1325 wm_adsp2_remove(&cs35l45->dsp);
1327 gpiod_set_value_cansleep(cs35l45->reset_gpio, 0);
1329 pm_runtime_put_noidle(cs35l45->dev);
1330 regulator_disable(cs35l45->vdd_a);
1332 regulator_disable(cs35l45->vdd_batt);