Lines Matching refs:x00
41 #define ADAU1372_REG_CLK_CTRL 0x00
982 regmap_write(regmap, ADAU1372_REG_MODE_MP(1), 0x00); /* SDATA OUT */
994 { ADAU1372_REG_CLK_CTRL, 0x00 },
995 { ADAU1372_REG_PLL(0), 0x00 },
996 { ADAU1372_REG_PLL(1), 0x00 },
997 { ADAU1372_REG_PLL(2), 0x00 },
998 { ADAU1372_REG_PLL(3), 0x00 },
999 { ADAU1372_REG_PLL(4), 0x00 },
1000 { ADAU1372_REG_PLL(5), 0x00 },
1009 { ADAU1372_REG_ASRC_MODE, 0x00 },
1012 { ADAU1372_REG_ADC_CTRL2, 0x00 },
1013 { ADAU1372_REG_ADC_CTRL3, 0x00 },
1014 { ADAU1372_REG_ADC_VOL(0), 0x00 },
1015 { ADAU1372_REG_ADC_VOL(1), 0x00 },
1016 { ADAU1372_REG_ADC_VOL(2), 0x00 },
1017 { ADAU1372_REG_ADC_VOL(3), 0x00 },
1022 { ADAU1372_REG_PGA_BOOST, 0x00 },
1023 { ADAU1372_REG_MICBIAS, 0x00 },
1025 { ADAU1372_REG_DAC_VOL(0), 0x00 },
1026 { ADAU1372_REG_DAC_VOL(1), 0x00 },
1028 { ADAU1372_REG_SAI0, 0x00 },
1029 { ADAU1372_REG_SAI1, 0x00 },
1030 { ADAU1372_REG_SOUT_CTRL, 0x00 },
1031 { ADAU1372_REG_MODE_MP(0), 0x00 },
1033 { ADAU1372_REG_MODE_MP(4), 0x00 },
1034 { ADAU1372_REG_MODE_MP(5), 0x00 },
1037 { ADAU1372_REG_DECIM_PWR, 0x00 },
1038 { ADAU1372_REG_INTERP_PWR, 0x00 },
1039 { ADAU1372_REG_BIAS_CTRL0, 0x00 },
1040 { ADAU1372_REG_BIAS_CTRL1, 0x00 },