Lines Matching defs:adau1372
23 #include "adau1372.h"
26 struct adau1372 {
575 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
581 adau1372->clock_provider = true;
585 adau1372->clock_provider = false;
629 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0);
630 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1,
640 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
656 slot_width = adau1372->slot_width;
672 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0);
673 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1);
681 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
687 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0,
689 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
690 adau1372->slot_width = 0;
713 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
717 if (adau1372->clock_provider)
718 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER;
720 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4;
724 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8;
730 adau1372->slot_width = width;
732 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0);
733 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1);
736 regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask);
743 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
751 return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1);
756 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
759 &adau1372->rate_constraints);
764 static void adau1372_enable_pll(struct adau1372 *adau1372)
769 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
774 ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val);
781 dev_err(adau1372->dev, "Failed to lock PLL\n");
784 static void adau1372_set_power(struct adau1372 *adau1372, bool enable)
786 if (adau1372->enabled == enable)
792 clk_prepare_enable(adau1372->mclk);
793 if (adau1372->pd_gpio)
794 gpiod_set_value(adau1372->pd_gpio, 0);
796 if (adau1372->switch_mode)
797 adau1372->switch_mode(adau1372->dev);
799 regcache_cache_only(adau1372->regmap, false);
805 if (adau1372->use_pll) {
806 adau1372_enable_pll(adau1372);
810 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
812 regcache_sync(adau1372->regmap);
814 if (adau1372->pd_gpio) {
820 gpiod_set_value(adau1372->pd_gpio, 1);
821 regcache_mark_dirty(adau1372->regmap);
823 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
826 clk_disable_unprepare(adau1372->mclk);
827 regcache_cache_only(adau1372->regmap, true);
830 adau1372->enabled = enable;
836 struct adau1372 *adau1372 = snd_soc_component_get_drvdata(component);
844 adau1372_set_power(adau1372, true);
847 adau1372_set_power(adau1372, false);
878 .name = "adau1372",
899 static int adau1372_setup_pll(struct adau1372 *adau1372, unsigned int rate)
910 regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]);
918 struct adau1372 *adau1372;
926 adau1372 = devm_kzalloc(dev, sizeof(*adau1372), GFP_KERNEL);
927 if (!adau1372)
930 adau1372->mclk = devm_clk_get(dev, "mclk");
931 if (IS_ERR(adau1372->mclk))
932 return PTR_ERR(adau1372->mclk);
934 adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
935 if (IS_ERR(adau1372->pd_gpio))
936 return PTR_ERR(adau1372->pd_gpio);
938 adau1372->regmap = regmap;
939 adau1372->switch_mode = switch_mode;
940 adau1372->dev = dev;
941 adau1372->rate_constraints.list = adau1372_rates;
942 adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates);
943 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
945 dev_set_drvdata(dev, adau1372);
952 rate = clk_get_rate(adau1372->mclk);
963 ret = adau1372_setup_pll(adau1372, rate);
966 adau1372->use_pll = true;