Lines Matching refs:info
96 static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
99 __raw_writel(val, info->regs + reg);
102 static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
105 return __raw_readl(info->regs + reg);
108 static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
112 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
113 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
115 clk_prepare_enable(info->mclk);
116 clk_prepare_enable(info->sclk);
117 clk_prepare_enable(info->lrclk);
120 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
128 ep93xx_i2s_write_reg(info, base_reg, 1);
133 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL,
138 static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
145 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0);
152 ep93xx_i2s_write_reg(info, base_reg, 0);
154 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
155 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
157 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
160 clk_disable_unprepare(info->lrclk);
161 clk_disable_unprepare(info->sclk);
162 clk_disable_unprepare(info->mclk);
176 struct ep93xx_i2s_info *info = dev_id;
179 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0);
186 while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) &
188 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0);
189 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0);
192 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1);
199 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
201 info->dma_params_tx.filter_data =
203 info->dma_params_rx.filter_data =
206 snd_soc_dai_init_dma_data(dai, &info->dma_params_tx,
207 &info->dma_params_rx);
215 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
217 ep93xx_i2s_enable(info, substream->stream);
225 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
227 ep93xx_i2s_disable(info, substream->stream);
233 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
238 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
299 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
300 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
301 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl);
302 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl);
310 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
332 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
334 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
344 div = clk_get_rate(info->mclk) / params_rate(params);
354 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
358 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
368 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
375 return clk_set_rate(info->mclk, freq);
381 struct ep93xx_i2s_info *info = snd_soc_component_get_drvdata(component);
386 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
387 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
394 struct ep93xx_i2s_info *info = snd_soc_component_get_drvdata(component);
399 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
400 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
446 struct ep93xx_i2s_info *info;
449 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
450 if (!info)
453 info->regs = devm_platform_ioremap_resource(pdev, 0);
454 if (IS_ERR(info->regs))
455 return PTR_ERR(info->regs);
463 pdev->name, info);
468 info->mclk = clk_get(&pdev->dev, "mclk");
469 if (IS_ERR(info->mclk)) {
470 err = PTR_ERR(info->mclk);
474 info->sclk = clk_get(&pdev->dev, "sclk");
475 if (IS_ERR(info->sclk)) {
476 err = PTR_ERR(info->sclk);
480 info->lrclk = clk_get(&pdev->dev, "lrclk");
481 if (IS_ERR(info->lrclk)) {
482 err = PTR_ERR(info->lrclk);
486 dev_set_drvdata(&pdev->dev, info);
500 clk_put(info->lrclk);
502 clk_put(info->sclk);
504 clk_put(info->mclk);
511 struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
513 clk_put(info->lrclk);
514 clk_put(info->sclk);
515 clk_put(info->mclk);