Lines Matching defs:acp_reg_write
123 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
141 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
144 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
152 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
156 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
169 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
170 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
172 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
173 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
176 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
177 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
188 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
309 acp_reg_write((offset + (page_idx * 8)),
315 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
318 acp_reg_write((offset + (page_idx * 8) + 4),
323 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
379 acp_reg_write(0x0, acp_mmio, ch_reg);
381 acp_reg_write(0x2, acp_mmio, res_reg);
386 acp_reg_write(val, acp_mmio, imr_reg);
387 acp_reg_write(0x1, acp_mmio, ch_reg);
409 acp_reg_write(val, acp_mmio, imr_reg);
410 acp_reg_write(0x0, acp_mmio, ch_reg);
422 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
450 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
469 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
478 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
491 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
540 acp_reg_write(val, acp_mmio, req_reg);
561 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
579 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
597 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
603 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
607 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
611 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
618 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
619 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
622 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
626 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
627 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
655 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
672 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
710 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
717 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM)) << 16,
724 acp_reg_write((intr_flag &
741 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
759 acp_reg_write((intr_flag &
820 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
897 acp_reg_write(val, adata->acp_mmio,
1241 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1391 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1403 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1417 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);