Lines Matching defs:hdspm
141 #include <sound/hdspm.h>
955 struct hdspm *hdspm;
981 struct hdspm {
1089 struct hdspm *hdspm);
1091 struct hdspm *hdspm);
1093 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1094 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1095 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1096 static int hdspm_autosync_ref(struct hdspm *hdspm);
1097 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1098 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1099 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1100 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm,
1104 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1105 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1106 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1107 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1109 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1110 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1111 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1125 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1127 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1134 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1137 writel(val, hdspm->iobase + reg);
1140 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1142 return readl(hdspm->iobase + reg);
1149 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1155 return hdspm->mixer->ch[chan].in[in];
1158 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1163 return hdspm->mixer->ch[chan].pb[pb];
1166 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1172 hdspm_write(hdspm,
1175 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1179 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1185 hdspm_write(hdspm,
1188 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1194 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1196 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1199 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1201 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1205 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1210 spin_lock_irqsave(&hdspm->lock, flags);
1211 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1212 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1215 spin_unlock_irqrestore(&hdspm->lock, flags);
1238 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1241 if (hdspm->control_register & HDSPM_QuadSpeed)
1243 else if (hdspm->control_register &
1251 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1256 switch (hdspm->io_type) {
1258 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1259 status = hdspm_read(hdspm, HDSPM_statusRegister);
1261 syncref = hdspm_autosync_ref(hdspm);
1265 if (hdspm_wc_sync_check(hdspm))
1266 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1278 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1279 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1286 if (hdspm_tco_sync_check(hdspm))
1287 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1295 status = hdspm_read(hdspm, HDSPM_statusRegister);
1329 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1330 status = hdspm_read(hdspm, HDSPM_statusRegister);
1379 return hdspm_rate_multiplier(hdspm, rate);
1425 syncref = hdspm_autosync_ref(hdspm);
1429 hdspm_tco_sync_check(hdspm));
1433 hdspm_sync_in_sync_check(hdspm));
1438 hdspm_get_pll_freq(hdspm));
1442 rate = hdspm_rate_multiplier(hdspm, rate);
1451 static int hdspm_get_latency(struct hdspm *hdspm)
1455 n = hdspm_decode_latency(hdspm->control_register);
1464 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1471 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1473 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1477 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1481 position = hdspm_read(hdspm, HDSPM_statusRegister);
1483 switch (hdspm->io_type) {
1491 (hdspm->period_bytes / 4) : 0;
1498 static inline void hdspm_start_audio(struct hdspm * s)
1504 static inline void hdspm_stop_audio(struct hdspm * s)
1511 static void hdspm_silence_playback(struct hdspm *hdspm)
1514 int n = hdspm->period_bytes;
1515 void *buf = hdspm->playback_buffer;
1526 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1565 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1572 switch (hdspm->io_type) {
1593 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1605 switch (hdspm->io_type) {
1625 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1629 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1636 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1640 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1649 dev_warn(hdspm->card->dev,
1656 hdspm_external_sample_rate(hdspm);
1658 if (hdspm_autosync_ref(hdspm) ==
1661 dev_warn(hdspm->card->dev,
1667 dev_warn(hdspm->card->dev,
1674 current_rate = hdspm->system_sample_rate;
1733 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1734 dev_err(hdspm->card->dev,
1738 hdspm->capture_pid, hdspm->playback_pid);
1742 hdspm->control_register &= ~HDSPM_FrequencyMask;
1743 hdspm->control_register |= rate_bits;
1744 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1748 hdspm_set_dds_value(hdspm, rate);
1750 if (AES32 == hdspm->io_type && rate != current_rate)
1751 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1753 hdspm->system_sample_rate = rate;
1756 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1757 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1758 hdspm->max_channels_in = hdspm->ss_in_channels;
1759 hdspm->max_channels_out = hdspm->ss_out_channels;
1760 hdspm->port_names_in = hdspm->port_names_in_ss;
1761 hdspm->port_names_out = hdspm->port_names_out_ss;
1763 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1764 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1765 hdspm->max_channels_in = hdspm->ds_in_channels;
1766 hdspm->max_channels_out = hdspm->ds_out_channels;
1767 hdspm->port_names_in = hdspm->port_names_in_ds;
1768 hdspm->port_names_out = hdspm->port_names_out_ds;
1770 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1771 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1772 hdspm->max_channels_in = hdspm->qs_in_channels;
1773 hdspm->max_channels_out = hdspm->qs_out_channels;
1774 hdspm->port_names_in = hdspm->port_names_in_qs;
1775 hdspm->port_names_out = hdspm->port_names_out_qs;
1785 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1799 hdspm_write_in_gain(hdspm, i, j, gain);
1800 hdspm_write_pb_gain(hdspm, i, j, gain);
1808 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1812 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1815 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1819 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1822 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1824 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1827 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1831 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1839 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1841 while (snd_hdspm_midi_input_available (hdspm, id))
1842 snd_hdspm_midi_read_byte (hdspm, id);
1858 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1868 snd_hdspm_midi_write_byte (hmidi->hdspm,
1888 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1894 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1902 snd_hdspm_midi_read_byte (hmidi->hdspm,
1909 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1910 hmidi->hdspm->control_register |= hmidi->ie;
1911 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1912 hmidi->hdspm->control_register);
1913 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1921 struct hdspm *hdspm;
1926 hdspm = hmidi->hdspm;
1928 spin_lock_irqsave (&hdspm->lock, flags);
1930 if (!(hdspm->control_register & hmidi->ie)) {
1931 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1932 hdspm->control_register |= hmidi->ie;
1935 hdspm->control_register &= ~hmidi->ie;
1938 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1939 spin_unlock_irqrestore (&hdspm->lock, flags);
1992 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
2054 struct hdspm *hdspm, int id)
2059 hdspm->midi[id].id = id;
2060 hdspm->midi[id].hdspm = hdspm;
2061 spin_lock_init (&hdspm->midi[id].lock);
2064 if (MADIface == hdspm->io_type) {
2066 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2067 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2068 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2069 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2070 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2071 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2073 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2074 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2075 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2076 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2077 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2078 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2081 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2082 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2083 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2084 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2085 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2086 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2087 } else if ((2 == id) && (MADI == hdspm->io_type)) {
2089 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2090 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2091 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2092 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2093 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2094 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2097 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2098 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2099 hdspm->midi[2].dataOut = -1;
2100 hdspm->midi[2].statusOut = -1;
2101 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2102 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2105 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2106 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2107 hdspm->midi[3].dataOut = -1;
2108 hdspm->midi[3].statusOut = -1;
2109 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2110 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2113 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2114 (MADIface == hdspm->io_type)))) {
2115 if ((id == 0) && (MADIface == hdspm->io_type)) {
2118 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2126 &hdspm->midi[id].rmidi);
2130 snprintf(hdspm->midi[id].rmidi->name,
2131 sizeof(hdspm->midi[id].rmidi->name),
2133 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2135 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2138 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2142 hdspm->midi[id].rmidi->info_flags |=
2151 &hdspm->midi[id].rmidi);
2155 snprintf(hdspm->midi[id].rmidi->name,
2156 sizeof(hdspm->midi[id].rmidi->name),
2158 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2160 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2164 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2173 struct hdspm *hdspm = container_of(work, struct hdspm, midi_work);
2176 while (i < hdspm->midiPorts) {
2177 if (hdspm->midi[i].pending)
2178 snd_hdspm_midi_input_read(&hdspm->midi[i]);
2192 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2196 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2197 rate = hdspm_calc_dds_value(hdspm, period);
2206 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2210 rate = hdspm_get_pll_freq(hdspm);
2214 if (0 == hdspm_system_clock_mode(hdspm)) {
2216 rate = hdspm->system_sample_rate;
2219 rate = hdspm_external_sample_rate(hdspm);
2221 rate = hdspm->system_sample_rate;
2256 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2258 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2266 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2271 hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]);
2279 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2283 switch (hdspm->io_type) {
2286 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2289 status = hdspm_read(hdspm, HDSPM_statusRegister);
2303 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2307 if (hdspm->tco) {
2308 switch (hdspm->io_type) {
2311 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2314 status = hdspm_read(hdspm, HDSPM_statusRegister);
2328 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2332 if (hdspm->tco) {
2333 switch (hdspm->io_type) {
2336 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2349 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2353 switch (hdspm->io_type) {
2355 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2367 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2369 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2381 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2383 int rate = hdspm_external_sample_rate(hdspm);
2416 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2418 switch (hdspm->io_type) {
2423 hdspm_get_wc_sample_rate(hdspm);
2427 hdspm_get_tco_sample_rate(hdspm);
2431 hdspm_get_sync_in_sample_rate(hdspm);
2435 hdspm_get_s1_sample_rate(hdspm,
2444 hdspm_get_wc_sample_rate(hdspm);
2448 hdspm_get_tco_sample_rate(hdspm);
2452 hdspm_get_sync_in_sample_rate(hdspm);
2456 hdspm_get_s1_sample_rate(hdspm,
2466 hdspm_get_wc_sample_rate(hdspm);
2470 hdspm_get_tco_sample_rate(hdspm);
2474 hdspm_get_sync_in_sample_rate(hdspm);
2478 hdspm_external_rate_to_enum(hdspm);
2482 hdspm_get_aes_sample_rate(hdspm,
2492 hdspm_external_rate_to_enum(hdspm);
2518 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2520 switch (hdspm->io_type) {
2523 if (hdspm->settings_register & HDSPM_c0Master)
2528 if (hdspm->control_register & HDSPM_ClockModeMaster)
2540 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2542 hdspm_set_toggle_setting(hdspm,
2543 (hdspm_is_raydat_or_aio(hdspm)) ?
2560 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2562 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2569 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2572 if (!snd_hdspm_use_is_exclusive(hdspm))
2581 hdspm_set_system_clock_mode(hdspm, val);
2597 static int hdspm_clock_source(struct hdspm * hdspm)
2599 switch (hdspm->system_sample_rate) {
2614 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2639 hdspm_set_rate(hdspm, rate, 1);
2652 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2654 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2661 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2665 if (!snd_hdspm_use_is_exclusive(hdspm))
2672 spin_lock_irq(&hdspm->lock);
2673 if (val != hdspm_clock_source(hdspm))
2674 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2677 spin_unlock_irq(&hdspm->lock);
2699 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2701 switch (hdspm->io_type) {
2703 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2720 if (hdspm->tco) {
2721 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2729 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2739 if (hdspm->tco) {
2740 switch ((hdspm->settings_register &
2753 switch ((hdspm->settings_register &
2769 if (hdspm->tco) {
2770 switch ((hdspm->settings_register &
2780 switch ((hdspm->settings_register &
2802 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2806 switch (hdspm->io_type) {
2808 hdspm->control_register &= ~HDSPM_SyncRefMask;
2813 hdspm->control_register |= HDSPM_SyncRef0;
2816 hdspm->control_register |= HDSPM_SyncRef1;
2819 hdspm->control_register |=
2823 hdspm->control_register |= HDSPM_SyncRef2;
2826 hdspm->control_register |=
2830 hdspm->control_register |=
2834 hdspm->control_register |=
2838 hdspm->control_register |= HDSPM_SyncRef3;
2841 hdspm->control_register |=
2852 hdspm->control_register &= ~HDSPM_SyncRefMask;
2853 if (hdspm->tco) {
2858 hdspm->control_register |= HDSPM_SyncRef0;
2861 hdspm->control_register |= HDSPM_SyncRef1;
2864 hdspm->control_register |=
2875 hdspm->control_register |= HDSPM_SyncRef0;
2878 hdspm->control_register |=
2889 if (hdspm->tco) {
2918 if (hdspm->tco) {
2941 switch (hdspm->io_type) {
2944 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2945 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2946 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2952 hdspm_write(hdspm, HDSPM_controlRegister,
2953 hdspm->control_register);
2963 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2965 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2973 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2974 int psf = hdspm_pref_sync_ref(hdspm);
2987 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2990 if (!snd_hdspm_use_is_exclusive(hdspm))
2997 else if (val >= hdspm->texts_autosync_items)
2998 val = hdspm->texts_autosync_items-1;
3000 spin_lock_irq(&hdspm->lock);
3001 if (val != hdspm_pref_sync_ref(hdspm))
3002 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
3004 spin_unlock_irq(&hdspm->lock);
3018 static int hdspm_autosync_ref(struct hdspm *hdspm)
3021 if (AES32 == hdspm->io_type) {
3023 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
3031 } else if (MADI == hdspm->io_type) {
3033 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3057 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3059 if (AES32 == hdspm->io_type) {
3064 } else if (MADI == hdspm->io_type) {
3076 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3078 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3107 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3108 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3148 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3153 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3182 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3184 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3197 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3201 if (hdspm_is_raydat_or_aio(hdspm))
3202 reg = hdspm->settings_register;
3204 reg = hdspm->control_register;
3209 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3214 if (hdspm_is_raydat_or_aio(hdspm)) {
3215 reg = &(hdspm->settings_register);
3218 reg = &(hdspm->control_register);
3227 hdspm_write(hdspm, target_reg, *reg);
3237 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3240 spin_lock_irq(&hdspm->lock);
3241 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3242 spin_unlock_irq(&hdspm->lock);
3249 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3254 if (!snd_hdspm_use_is_exclusive(hdspm))
3257 spin_lock_irq(&hdspm->lock);
3258 change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3259 hdspm_set_toggle_setting(hdspm, regmask, val);
3260 spin_unlock_irq(&hdspm->lock);
3273 static int hdspm_input_select(struct hdspm * hdspm)
3275 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3278 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3281 hdspm->control_register |= HDSPM_InputSelect0;
3283 hdspm->control_register &= ~HDSPM_InputSelect0;
3284 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3300 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3302 spin_lock_irq(&hdspm->lock);
3303 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3304 spin_unlock_irq(&hdspm->lock);
3311 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3315 if (!snd_hdspm_use_is_exclusive(hdspm))
3318 spin_lock_irq(&hdspm->lock);
3319 change = (int) val != hdspm_input_select(hdspm);
3320 hdspm_set_input_select(hdspm, val);
3321 spin_unlock_irq(&hdspm->lock);
3335 static int hdspm_ds_wire(struct hdspm * hdspm)
3337 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3340 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3343 hdspm->control_register |= HDSPM_DS_DoubleWire;
3345 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3346 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3362 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3364 spin_lock_irq(&hdspm->lock);
3365 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3366 spin_unlock_irq(&hdspm->lock);
3373 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3377 if (!snd_hdspm_use_is_exclusive(hdspm))
3380 spin_lock_irq(&hdspm->lock);
3381 change = (int) val != hdspm_ds_wire(hdspm);
3382 hdspm_set_ds_wire(hdspm, val);
3383 spin_unlock_irq(&hdspm->lock);
3397 static int hdspm_qs_wire(struct hdspm * hdspm)
3399 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3401 if (hdspm->control_register & HDSPM_QS_QuadWire)
3406 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3408 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3413 hdspm->control_register |= HDSPM_QS_DoubleWire;
3416 hdspm->control_register |= HDSPM_QS_QuadWire;
3419 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3435 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3437 spin_lock_irq(&hdspm->lock);
3438 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3439 spin_unlock_irq(&hdspm->lock);
3446 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3450 if (!snd_hdspm_use_is_exclusive(hdspm))
3457 spin_lock_irq(&hdspm->lock);
3458 change = val != hdspm_qs_wire(hdspm);
3459 hdspm_set_qs_wire(hdspm, val);
3460 spin_unlock_irq(&hdspm->lock);
3473 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3475 u32 reg = hdspm->settings_register & (regmask * 3);
3479 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3481 hdspm->settings_register &= ~(regmask * 3);
3482 hdspm->settings_register |= (regmask * mode);
3483 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3510 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3513 spin_lock_irq(&hdspm->lock);
3514 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3515 spin_unlock_irq(&hdspm->lock);
3522 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3527 if (!snd_hdspm_use_is_exclusive(hdspm))
3535 spin_lock_irq(&hdspm->lock);
3536 change = val != hdspm_tristate(hdspm, regmask);
3537 hdspm_set_tristate(hdspm, val, regmask);
3538 spin_unlock_irq(&hdspm->lock);
3551 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3553 if (hdspm->control_register & HDSPM_QuadSpeed)
3555 if (hdspm->control_register & HDSPM_DoubleSpeed)
3560 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3562 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3567 hdspm->control_register |= HDSPM_DoubleSpeed;
3570 hdspm->control_register |= HDSPM_QuadSpeed;
3573 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3589 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3591 spin_lock_irq(&hdspm->lock);
3592 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3593 spin_unlock_irq(&hdspm->lock);
3600 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3604 if (!snd_hdspm_use_is_exclusive(hdspm))
3611 spin_lock_irq(&hdspm->lock);
3612 change = val != hdspm_madi_speedmode(hdspm);
3613 hdspm_set_madi_speedmode(hdspm, val);
3614 spin_unlock_irq(&hdspm->lock);
3644 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3660 spin_lock_irq(&hdspm->lock);
3663 hdspm_read_pb_gain(hdspm, destination,
3667 hdspm_read_in_gain(hdspm, destination, source);
3669 spin_unlock_irq(&hdspm->lock);
3677 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3683 if (!snd_hdspm_use_is_exclusive(hdspm))
3696 spin_lock_irq(&hdspm->lock);
3699 change = gain != hdspm_read_pb_gain(hdspm, destination,
3703 change = gain != hdspm_read_in_gain(hdspm, destination,
3708 hdspm_write_pb_gain(hdspm, destination,
3712 hdspm_write_in_gain(hdspm, destination, source,
3715 spin_unlock_irq(&hdspm->lock);
3748 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3756 spin_lock_irq(&hdspm->lock);
3758 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3759 spin_unlock_irq(&hdspm->lock);
3767 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3772 if (!snd_hdspm_use_is_exclusive(hdspm))
3782 spin_lock_irq(&hdspm->lock);
3784 gain != hdspm_read_pb_gain(hdspm, channel,
3787 hdspm_write_pb_gain(hdspm, channel, channel,
3789 spin_unlock_irq(&hdspm->lock);
3829 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3833 switch (hdspm->io_type) {
3835 status = hdspm_read(hdspm, HDSPM_statusRegister);
3845 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3856 status = hdspm_read(hdspm, HDSPM_statusRegister);
3873 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3875 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3886 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3890 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3903 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3907 switch (hdspm->io_type) {
3910 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3916 status = hdspm_read(hdspm, HDSPM_statusRegister);
3922 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3939 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3942 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3954 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3957 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3963 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3967 if (hdspm->tco) {
3968 switch (hdspm->io_type) {
3970 status = hdspm_read(hdspm, HDSPM_statusRegister);
3979 status = hdspm_read(hdspm, HDSPM_statusRegister);
3989 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
4009 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4012 switch (hdspm->io_type) {
4016 val = hdspm_wc_sync_check(hdspm); break;
4018 val = hdspm_tco_sync_check(hdspm); break;
4020 val = hdspm_sync_in_sync_check(hdspm); break;
4022 val = hdspm_s1_sync_check(hdspm,
4030 val = hdspm_wc_sync_check(hdspm); break;
4032 val = hdspm_tco_sync_check(hdspm); break;
4034 val = hdspm_sync_in_sync_check(hdspm); break;
4036 val = hdspm_s1_sync_check(hdspm,
4044 val = hdspm_wc_sync_check(hdspm); break;
4046 val = hdspm_madi_sync_check(hdspm); break;
4048 val = hdspm_tco_sync_check(hdspm); break;
4050 val = hdspm_sync_in_sync_check(hdspm); break;
4055 val = hdspm_madi_sync_check(hdspm); /* MADI */
4061 val = hdspm_wc_sync_check(hdspm); break;
4063 val = hdspm_tco_sync_check(hdspm); break;
4065 val = hdspm_sync_in_sync_check(hdspm); break;
4067 val = hdspm_aes_sync_check(hdspm,
4074 if (hdspm->tco) {
4078 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4082 val = hdspm_tco_input_check(hdspm,
4102 static void hdspm_tco_write(struct hdspm *hdspm)
4106 switch (hdspm->tco->input) {
4117 switch (hdspm->tco->framerate) {
4141 switch (hdspm->tco->wordclock) {
4152 switch (hdspm->tco->samplerate) {
4163 switch (hdspm->tco->pull) {
4180 if (1 == hdspm->tco->term) {
4184 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4185 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4186 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4187 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4214 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4216 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4224 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4226 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4227 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4229 hdspm_tco_write(hdspm);
4261 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4263 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4271 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4273 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4274 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4276 hdspm_tco_write(hdspm);
4306 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4308 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4316 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4318 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4319 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4321 hdspm_tco_write(hdspm);
4353 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4355 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4363 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4365 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4366 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4368 hdspm_tco_write(hdspm);
4399 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4401 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4409 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4411 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4412 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4414 hdspm_tco_write(hdspm);
4449 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4451 ucontrol->value.integer.value[0] = hdspm->tco->term;
4460 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4462 if (hdspm->tco->term != ucontrol->value.integer.value[0]) {
4463 hdspm->tco->term = ucontrol->value.integer.value[0];
4465 hdspm_tco_write(hdspm);
4639 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4643 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4644 if (hdspm->system_sample_rate > 48000) {
4645 hdspm->playback_mixer_ctls[i]->vd[0].access =
4650 hdspm->playback_mixer_ctls[i]->vd[0].access =
4654 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4656 &hdspm->playback_mixer_ctls[i]->id);
4664 struct hdspm *hdspm)
4671 switch (hdspm->io_type) {
4697 snd_ctl_new1(&list[idx], hdspm));
4706 if (hdspm->system_sample_rate >= 128000) {
4707 limit = hdspm->qs_out_channels;
4708 } else if (hdspm->system_sample_rate >= 64000) {
4709 limit = hdspm->ds_out_channels;
4711 limit = hdspm->ss_out_channels;
4715 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4719 hdspm->playback_mixer_ctls[idx] = kctl;
4723 if (hdspm->tco) {
4729 snd_ctl_new1(&list[idx], hdspm));
4746 struct hdspm *hdspm = entry->private_data;
4755 status = hdspm_read(hdspm, HDSPM_statusRegister);
4756 control = hdspm->control_register;
4761 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4800 switch (hdspm->io_type) {
4813 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4829 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4858 struct hdspm *hdspm = entry->private_data;
4866 status = hdspm_read(hdspm, HDSPM_statusRegister);
4867 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4870 hdspm->card_name, hdspm->card->number + 1,
4871 hdspm->firmware_rev,
4877 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4878 hdspm->serial);
4881 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4890 hdspm->irq_count);
4897 (2 * (int)hdspm->period_bytes),
4899 (2 * (int)hdspm->period_bytes),
4900 (long) hdspm_hw_pointer(hdspm) * 4);
4904 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4905 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4906 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4907 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4910 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4911 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4915 hdspm->control_register, hdspm->control2_register,
4921 x = hdspm_get_latency(hdspm);
4925 x, (unsigned long) hdspm->period_bytes);
4928 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4933 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4934 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4935 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4938 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4944 switch (hdspm_pref_sync_ref(hdspm)) {
4965 hdspm->system_sample_rate);
4979 switch (hdspm_autosync_ref(hdspm)) {
5001 autosync_ref, hdspm_external_sample_rate(hdspm),
5020 struct hdspm *hdspm = entry->private_data;
5029 status = hdspm_read(hdspm, HDSPM_statusRegister);
5030 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5031 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5034 hdspm->card_name, hdspm->card->number + 1,
5035 hdspm->firmware_rev);
5038 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5047 hdspm->irq_count);
5054 (2 * (int)hdspm->period_bytes),
5056 (2 * (int)hdspm->period_bytes),
5057 (long) hdspm_hw_pointer(hdspm) * 4);
5061 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5062 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5063 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5064 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5067 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5068 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5072 hdspm->control_register, hdspm->control2_register,
5077 x = hdspm_get_latency(hdspm);
5081 x, (unsigned long) hdspm->period_bytes);
5084 (hdspm->
5089 (hdspm->
5091 (hdspm->
5093 (hdspm->
5097 pref_syncref = hdspm_pref_sync_ref(hdspm);
5105 hdspm->system_sample_rate);
5108 hdspm->control_register & HDSPM_DS_DoubleWire?
5111 hdspm->control_register & HDSPM_QS_DoubleWire?
5113 hdspm->control_register & HDSPM_QS_QuadWire?
5133 switch (hdspm_autosync_ref(hdspm)) {
5173 struct hdspm *hdspm = entry->private_data;
5177 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5178 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5179 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5189 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5191 hdspm_get_system_sample_rate(hdspm));
5231 struct hdspm *hdspm = entry->private_data;
5238 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5248 struct hdspm *hdspm = entry->private_data;
5251 snd_iprintf(buffer, "# generated by hdspm\n");
5253 for (i = 0; i < hdspm->max_channels_in; i++) {
5254 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5261 struct hdspm *hdspm = entry->private_data;
5264 snd_iprintf(buffer, "# generated by hdspm\n");
5266 for (i = 0; i < hdspm->max_channels_out; i++) {
5267 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5272 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5276 switch (hdspm->io_type) {
5293 snd_card_ro_proc_new(hdspm->card, "hdspm", hdspm, read);
5294 snd_card_ro_proc_new(hdspm->card, "ports.in", hdspm,
5296 snd_card_ro_proc_new(hdspm->card, "ports.out", hdspm,
5300 /* debug file to read all hdspm registers */
5301 snd_card_ro_proc_new(hdspm->card, "debug", hdspm,
5307 hdspm intitialize
5310 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5312 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5318 hdspm->settings_register = 0;
5320 switch (hdspm->io_type) {
5323 hdspm->control_register =
5329 hdspm->settings_register = 0x1 + 0x1000;
5332 hdspm->control_register =
5337 hdspm->control_register =
5346 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5348 if (AES32 == hdspm->io_type) {
5351 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5353 hdspm->control2_register = 0;
5356 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5358 hdspm_compute_period_size(hdspm);
5362 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5364 if (hdspm_is_raydat_or_aio(hdspm))
5365 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5368 hdspm_set_rate(hdspm, 48000, 1);
5380 struct hdspm *hdspm = (struct hdspm *) dev_id;
5385 status = hdspm_read(hdspm, HDSPM_statusRegister);
5403 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n",
5404 now-hdspm->last_interrupt, status & 0xFFC0);
5405 hdspm->last_interrupt = now;
5411 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5412 hdspm->irq_count++;
5416 if (hdspm->capture_substream)
5417 snd_pcm_period_elapsed(hdspm->capture_substream);
5419 if (hdspm->playback_substream)
5420 snd_pcm_period_elapsed(hdspm->playback_substream);
5425 while (i < hdspm->midiPorts) {
5426 if ((hdspm_read(hdspm,
5427 hdspm->midi[i].statusIn) & 0xff) &&
5428 (status & hdspm->midi[i].irq)) {
5432 hdspm->control_register &= ~hdspm->midi[i].ie;
5433 hdspm_write(hdspm, HDSPM_controlRegister,
5434 hdspm->control_register);
5435 hdspm->midi[i].pending = 1;
5443 queue_work(system_highpri_wq, &hdspm->midi_work);
5457 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5458 return hdspm_hw_pointer(hdspm);
5465 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5469 other = hdspm->capture_substream;
5471 other = hdspm->playback_substream;
5473 if (hdspm->running)
5474 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5494 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5500 spin_lock_irq(&hdspm->lock);
5503 this_pid = hdspm->playback_pid;
5504 other_pid = hdspm->capture_pid;
5506 this_pid = hdspm->capture_pid;
5507 other_pid = hdspm->playback_pid;
5517 if (params_rate(params) != hdspm->system_sample_rate) {
5518 spin_unlock_irq(&hdspm->lock);
5524 if (params_period_size(params) != hdspm->period_bytes / 4) {
5525 spin_unlock_irq(&hdspm->lock);
5533 spin_unlock_irq(&hdspm->lock);
5537 spin_lock_irq(&hdspm->lock);
5538 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5540 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err);
5541 spin_unlock_irq(&hdspm->lock);
5546 spin_unlock_irq(&hdspm->lock);
5548 err = hdspm_set_interrupt_interval(hdspm,
5551 dev_info(hdspm->card->dev,
5568 dev_info(hdspm->card->dev,
5576 int c = hdspm->channel_map_out[i];
5580 hdspm_set_channel_dma_addr(hdspm, substream,
5583 snd_hdspm_enable_out(hdspm, c, 1);
5586 hdspm->playback_buffer =
5588 dev_dbg(hdspm->card->dev,
5590 hdspm->playback_buffer);
5593 int c = hdspm->channel_map_in[i];
5597 hdspm_set_channel_dma_addr(hdspm, substream,
5600 snd_hdspm_enable_in(hdspm, c, 1);
5603 hdspm->capture_buffer =
5605 dev_dbg(hdspm->card->dev,
5607 hdspm->capture_buffer);
5611 dev_dbg(hdspm->card->dev,
5618 dev_dbg(hdspm->card->dev,
5632 if (hdspm->io_type == AES32) {
5639 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5640 dev_info(hdspm->card->dev,
5643 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5645 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5646 dev_info(hdspm->card->dev,
5649 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5651 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5659 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5665 snd_hdspm_enable_out(hdspm, i, 0);
5667 hdspm->playback_buffer = NULL;
5670 snd_hdspm_enable_in(hdspm, i, 0);
5672 hdspm->capture_buffer = NULL;
5684 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5688 if (snd_BUG_ON(channel >= hdspm->max_channels_out)) {
5689 dev_info(hdspm->card->dev,
5695 channel = array_index_nospec(channel, hdspm->max_channels_out);
5696 if (hdspm->channel_map_out[channel] < 0) {
5697 dev_info(hdspm->card->dev,
5703 info->offset = hdspm->channel_map_out[channel] *
5706 if (snd_BUG_ON(channel >= hdspm->max_channels_in)) {
5707 dev_info(hdspm->card->dev,
5713 channel = array_index_nospec(channel, hdspm->max_channels_in);
5714 if (hdspm->channel_map_in[channel] < 0) {
5715 dev_info(hdspm->card->dev,
5721 info->offset = hdspm->channel_map_in[channel] *
5752 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5756 spin_lock(&hdspm->lock);
5757 running = hdspm->running;
5767 spin_unlock(&hdspm->lock);
5771 other = hdspm->capture_substream;
5773 other = hdspm->playback_substream;
5791 hdspm_silence_playback(hdspm);
5795 hdspm_silence_playback(hdspm);
5799 hdspm_silence_playback(hdspm);
5803 if (!hdspm->running && running)
5804 hdspm_start_audio(hdspm);
5805 else if (hdspm->running && !running)
5806 hdspm_stop_audio(hdspm);
5807 hdspm->running = running;
5808 spin_unlock(&hdspm->lock);
5871 struct hdspm *hdspm = rule->private;
5879 .min = hdspm->qs_in_channels,
5880 .max = hdspm->qs_in_channels,
5886 .min = hdspm->ds_in_channels,
5887 .max = hdspm->ds_in_channels,
5893 .min = hdspm->ss_in_channels,
5894 .max = hdspm->ss_in_channels,
5906 struct hdspm *hdspm = rule->private;
5914 .min = hdspm->qs_out_channels,
5915 .max = hdspm->qs_out_channels,
5921 .min = hdspm->ds_out_channels,
5922 .max = hdspm->ds_out_channels,
5928 .min = hdspm->ss_out_channels,
5929 .max = hdspm->ss_out_channels,
5941 struct hdspm *hdspm = rule->private;
5947 if (c->min >= hdspm->ss_in_channels) {
5954 } else if (c->max <= hdspm->qs_in_channels) {
5961 } else if (c->max <= hdspm->ds_in_channels) {
5975 struct hdspm *hdspm = rule->private;
5981 if (c->min >= hdspm->ss_out_channels) {
5988 } else if (c->max <= hdspm->qs_out_channels) {
5995 } else if (c->max <= hdspm->ds_out_channels) {
6011 struct hdspm *hdspm = rule->private;
6015 list[0] = hdspm->qs_in_channels;
6016 list[1] = hdspm->ds_in_channels;
6017 list[2] = hdspm->ss_in_channels;
6025 struct hdspm *hdspm = rule->private;
6029 list[0] = hdspm->qs_out_channels;
6030 list[1] = hdspm->ds_out_channels;
6031 list[2] = hdspm->ss_out_channels;
6049 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6053 spin_lock_irq(&hdspm->lock);
6059 if (!hdspm->capture_substream)
6060 hdspm_stop_audio(hdspm);
6062 hdspm->playback_pid = current->pid;
6063 hdspm->playback_substream = substream;
6065 if (!hdspm->playback_substream)
6066 hdspm_stop_audio(hdspm);
6068 hdspm->capture_pid = current->pid;
6069 hdspm->capture_substream = substream;
6072 spin_unlock_irq(&hdspm->lock);
6077 switch (hdspm->io_type) {
6098 if (AES32 == hdspm->io_type) {
6106 snd_hdspm_hw_rule_rate_in_channels), hdspm,
6112 snd_hdspm_hw_rule_in_channels), hdspm,
6117 snd_hdspm_hw_rule_in_channels_rate), hdspm,
6125 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6128 spin_lock_irq(&hdspm->lock);
6131 hdspm->playback_pid = -1;
6132 hdspm->playback_substream = NULL;
6134 hdspm->capture_pid = -1;
6135 hdspm->capture_substream = NULL;
6138 spin_unlock_irq(&hdspm->lock);
6153 struct hdspm *hdspm = hw->private_data;
6167 levels = &hdspm->peak_rms;
6170 readl(hdspm->iobase +
6173 readl(hdspm->iobase +
6176 readl(hdspm->iobase +
6180 ((uint64_t) readl(hdspm->iobase +
6182 (uint64_t) readl(hdspm->iobase +
6185 ((uint64_t)readl(hdspm->iobase +
6187 (uint64_t)readl(hdspm->iobase +
6190 ((uint64_t)readl(hdspm->iobase +
6192 (uint64_t)readl(hdspm->iobase +
6196 if (hdspm->system_sample_rate > 96000) {
6198 } else if (hdspm->system_sample_rate > 48000) {
6203 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6207 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu
6215 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6216 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6253 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6262 spin_lock_irq(&hdspm->lock);
6263 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6264 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6266 info.system_sample_rate = hdspm->system_sample_rate;
6268 hdspm_external_sample_rate(hdspm);
6269 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6270 info.clock_source = hdspm_clock_source(hdspm);
6271 info.autosync_ref = hdspm_autosync_ref(hdspm);
6272 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6274 spin_unlock_irq(&hdspm->lock);
6282 status.card_type = hdspm->io_type;
6284 status.autosync_source = hdspm_autosync_ref(hdspm);
6287 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6289 switch (hdspm->io_type) {
6293 hdspm_wc_sync_check(hdspm);
6295 hdspm_madi_sync_check(hdspm);
6297 hdspm_tco_sync_check(hdspm);
6299 hdspm_sync_in_sync_check(hdspm);
6302 hdspm_read(hdspm, HDSPM_statusRegister);
6324 hdspm_version.card_type = hdspm->io_type;
6325 strscpy(hdspm_version.cardname, hdspm->card_name,
6327 hdspm_version.serial = hdspm->serial;
6328 hdspm_version.firmware_rev = hdspm->firmware_rev;
6330 if (hdspm->tco)
6341 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6364 struct hdspm *hdspm)
6373 hdspm->hwdep = hw;
6374 hw->private_data = hdspm;
6389 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6394 pcm = hdspm->pcm;
6399 &hdspm->pci->dev,
6401 dev_dbg(hdspm->card->dev, " Preallocated %zd Bytes\n", wanted);
6407 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm,
6414 hdspm_write(hdspm, reg + 4 * i,
6421 struct hdspm *hdspm)
6426 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6430 hdspm->pcm = pcm;
6431 pcm->private_data = hdspm;
6432 strcpy(pcm->name, hdspm->card_name);
6441 err = snd_hdspm_preallocate_memory(hdspm);
6448 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6452 for (i = 0; i < hdspm->midiPorts; i++)
6453 snd_hdspm_flush_midi_input(hdspm, i);
6457 struct hdspm *hdspm)
6462 err = snd_hdspm_create_pcm(card, hdspm);
6467 while (i < hdspm->midiPorts) {
6468 err = snd_hdspm_create_midi(card, hdspm, i);
6475 err = snd_hdspm_create_controls(card, hdspm);
6479 err = snd_hdspm_create_hwdep(card, hdspm);
6484 snd_hdspm_proc_init(hdspm);
6486 hdspm->system_sample_rate = -1;
6487 hdspm->last_external_sample_rate = -1;
6488 hdspm->last_internal_sample_rate = -1;
6489 hdspm->playback_pid = -1;
6490 hdspm->capture_pid = -1;
6491 hdspm->capture_substream = NULL;
6492 hdspm->playback_substream = NULL;
6495 err = snd_hdspm_set_defaults(hdspm);
6500 hdspm_update_simple_mixer_controls(hdspm);
6516 struct hdspm *hdspm)
6519 struct pci_dev *pci = hdspm->pci;
6523 hdspm->irq = -1;
6524 hdspm->card = card;
6526 spin_lock_init(&hdspm->lock);
6527 INIT_WORK(&hdspm->midi_work, hdspm_midi_work);
6529 pci_read_config_word(hdspm->pci,
6530 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6535 switch (hdspm->firmware_rev) {
6537 hdspm->io_type = RayDAT;
6538 hdspm->card_name = "RME RayDAT";
6539 hdspm->midiPorts = 2;
6542 hdspm->io_type = AIO;
6543 hdspm->card_name = "RME AIO";
6544 hdspm->midiPorts = 1;
6547 hdspm->io_type = MADIface;
6548 hdspm->card_name = "RME MADIface";
6549 hdspm->midiPorts = 1;
6552 if ((hdspm->firmware_rev == 0xf0) ||
6553 ((hdspm->firmware_rev >= 0xe6) &&
6554 (hdspm->firmware_rev <= 0xea))) {
6555 hdspm->io_type = AES32;
6556 hdspm->card_name = "RME AES32";
6557 hdspm->midiPorts = 2;
6558 } else if ((hdspm->firmware_rev == 0xd2) ||
6559 ((hdspm->firmware_rev >= 0xc8) &&
6560 (hdspm->firmware_rev <= 0xcf))) {
6561 hdspm->io_type = MADI;
6562 hdspm->card_name = "RME MADI";
6563 hdspm->midiPorts = 3;
6567 hdspm->firmware_rev);
6576 pci_set_master(hdspm->pci);
6578 err = pcim_iomap_regions(pci, 1 << 0, "hdspm");
6582 hdspm->port = pci_resource_start(pci, 0);
6584 hdspm->iobase = pcim_iomap_table(pci)[0];
6586 (unsigned long)hdspm->iobase, hdspm->port,
6587 hdspm->port + io_extent - 1);
6590 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6597 hdspm->irq = pci->irq;
6598 card->sync_irq = hdspm->irq;
6601 sizeof(*hdspm->mixer));
6602 hdspm->mixer = devm_kzalloc(&pci->dev, sizeof(*hdspm->mixer), GFP_KERNEL);
6603 if (!hdspm->mixer)
6606 hdspm->port_names_in = NULL;
6607 hdspm->port_names_out = NULL;
6609 switch (hdspm->io_type) {
6611 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6612 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6613 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6615 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6617 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6619 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6621 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6623 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6625 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6628 hdspm->max_channels_out = hdspm->max_channels_in =
6630 hdspm->port_names_in = hdspm->port_names_out =
6632 hdspm->channel_map_in = hdspm->channel_map_out =
6639 hdspm->ss_in_channels = hdspm->ss_out_channels =
6641 hdspm->ds_in_channels = hdspm->ds_out_channels =
6643 hdspm->qs_in_channels = hdspm->qs_out_channels =
6646 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6648 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6650 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6653 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6655 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6657 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6662 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6663 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6664 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6665 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6666 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6667 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6669 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6671 hdspm->ss_in_channels += 4;
6672 hdspm->ds_in_channels += 4;
6673 hdspm->qs_in_channels += 4;
6676 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6678 hdspm->ss_out_channels += 4;
6679 hdspm->ds_out_channels += 4;
6680 hdspm->qs_out_channels += 4;
6683 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6684 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6685 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6687 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6688 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6689 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6691 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6692 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6693 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6694 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6695 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6696 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6701 hdspm->ss_in_channels = hdspm->ss_out_channels =
6703 hdspm->ds_in_channels = hdspm->ds_out_channels =
6705 hdspm->qs_in_channels = hdspm->qs_out_channels =
6708 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6709 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6711 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6713 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6715 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6717 hdspm->channel_map_in = hdspm->channel_map_out =
6720 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6722 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6724 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6733 switch (hdspm->io_type) {
6736 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6738 hdspm->midiPorts++;
6739 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL);
6740 if (hdspm->tco)
6741 hdspm_tco_write(hdspm);
6745 hdspm->tco = NULL;
6751 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6752 hdspm->midiPorts++;
6753 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL);
6754 if (hdspm->tco)
6755 hdspm_tco_write(hdspm);
6759 hdspm->tco = NULL;
6764 hdspm->tco = NULL;
6768 switch (hdspm->io_type) {
6770 if (hdspm->tco) {
6771 hdspm->texts_autosync = texts_autosync_aes_tco;
6772 hdspm->texts_autosync_items =
6775 hdspm->texts_autosync = texts_autosync_aes;
6776 hdspm->texts_autosync_items =
6782 if (hdspm->tco) {
6783 hdspm->texts_autosync = texts_autosync_madi_tco;
6784 hdspm->texts_autosync_items = 4;
6786 hdspm->texts_autosync = texts_autosync_madi;
6787 hdspm->texts_autosync_items = 3;
6796 if (hdspm->tco) {
6797 hdspm->texts_autosync = texts_autosync_raydat_tco;
6798 hdspm->texts_autosync_items = 9;
6800 hdspm->texts_autosync = texts_autosync_raydat;
6801 hdspm->texts_autosync_items = 8;
6806 if (hdspm->tco) {
6807 hdspm->texts_autosync = texts_autosync_aio_tco;
6808 hdspm->texts_autosync_items = 6;
6810 hdspm->texts_autosync = texts_autosync_aio;
6811 hdspm->texts_autosync_items = 5;
6817 if (hdspm->io_type != MADIface) {
6818 hdspm->serial = (hdspm_read(hdspm,
6829 if (!id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6831 "HDSPMx%06x", hdspm->serial);
6837 err = snd_hdspm_create_alsa_devices(card, hdspm);
6841 snd_hdspm_initialize_midi_flush(hdspm);
6849 struct hdspm *hdspm = card->private_data;
6851 if (hdspm->port) {
6852 cancel_work_sync(&hdspm->midi_work);
6855 hdspm->control_register &=
6859 hdspm_write(hdspm, HDSPM_controlRegister,
6860 hdspm->control_register);
6869 struct hdspm *hdspm;
6881 THIS_MODULE, sizeof(*hdspm), &card);
6885 hdspm = card->private_data;
6887 hdspm->dev = dev;
6888 hdspm->pci = pci;
6890 err = snd_hdspm_create(card, hdspm);
6894 if (hdspm->io_type != MADIface) {
6896 hdspm->card_name, hdspm->serial);
6899 hdspm->card_name, hdspm->serial,
6900 hdspm->port, hdspm->irq);
6903 hdspm->card_name);
6906 hdspm->card_name, hdspm->port, hdspm->irq);