Lines Matching defs:wcreg
214 u32 wcreg; /* cached write control register value */
256 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
257 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
513 writel(rme96->wcreg | RME96_WCR_PD,
515 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
521 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
522 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
530 rme96->wcreg |= RME96_WCR_MONITOR_0;
532 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
535 rme96->wcreg |= RME96_WCR_MONITOR_1;
537 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
539 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
546 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
547 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
556 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
560 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
564 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
568 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
574 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
646 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
655 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
656 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
670 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
679 ds = rme96->wcreg & RME96_WCR_DS;
682 rme96->wcreg &= ~RME96_WCR_DS;
683 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
687 rme96->wcreg &= ~RME96_WCR_DS;
688 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
692 rme96->wcreg &= ~RME96_WCR_DS;
693 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
697 rme96->wcreg |= RME96_WCR_DS;
698 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
702 rme96->wcreg |= RME96_WCR_DS;
703 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
707 rme96->wcreg |= RME96_WCR_DS;
708 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
714 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
715 (ds && !(rme96->wcreg & RME96_WCR_DS)))
721 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
775 rme96->wcreg &= ~RME96_WCR_MASTER;
780 rme96->wcreg |= RME96_WCR_MASTER;
785 rme96->wcreg |= RME96_WCR_MASTER;
791 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
802 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
814 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
818 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
822 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
834 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
863 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
873 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
874 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
891 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
894 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
904 rme96->wcreg &= ~RME96_WCR_MODE24;
907 rme96->wcreg |= RME96_WCR_MODE24;
912 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
921 rme96->wcreg &= ~RME96_WCR_MODE24_2;
924 rme96->wcreg |= RME96_WCR_MODE24_2;
929 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
939 rme96->wcreg &= ~RME96_WCR_ISEL;
942 rme96->wcreg |= RME96_WCR_ISEL;
948 rme96->wcreg &= ~RME96_WCR_IDIS;
949 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
968 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1000 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1001 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1002 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1091 rme96->wcreg |= RME96_WCR_START;
1093 rme96->wcreg &= ~RME96_WCR_START;
1095 rme96->wcreg |= RME96_WCR_START_2;
1097 rme96->wcreg &= ~RME96_WCR_START_2;
1098 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1172 rme96->wcreg &= ~RME96_WCR_ADAT;
1173 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1178 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1242 rme96->wcreg |= RME96_WCR_ADAT;
1243 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1248 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1311 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1642 rme96->wcreg =
1650 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1700 if (rme96->wcreg & RME96_WCR_IDIS) {
1703 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1737 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1744 if (rme96->wcreg & RME96_WCR_SEL) {
1751 if (rme96->wcreg & RME96_WCR_MODE24) {
1758 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1767 if (rme96->wcreg & RME96_WCR_PRO) {
1772 if (rme96->wcreg & RME96_WCR_EMP) {
1777 if (rme96->wcreg & RME96_WCR_DOLBY) {
1834 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1847 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1848 change = val != rme96->wcreg;
1849 rme96->wcreg = val;
2147 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2148 rme96->wcreg |= val;
2149 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);