Lines Matching refs:chip
73 static int corb_send_verb(struct lola *chip, unsigned int nid,
80 chip->last_cmd_nid = nid;
81 chip->last_verb = verb;
82 chip->last_data = data;
83 chip->last_extdata = extdata;
86 spin_lock_irqsave(&chip->reg_lock, flags);
87 if (chip->rirb.cmds < LOLA_CORB_ENTRIES - 1) {
88 unsigned int wp = chip->corb.wp + 1;
90 chip->corb.wp = wp;
91 chip->corb.buf[wp * 2] = cpu_to_le32(data);
92 chip->corb.buf[wp * 2 + 1] = cpu_to_le32(extdata);
93 lola_writew(chip, BAR0, CORBWP, wp);
94 chip->rirb.cmds++;
98 spin_unlock_irqrestore(&chip->reg_lock, flags);
102 static void lola_queue_unsol_event(struct lola *chip, unsigned int res,
105 lola_update_ext_clock_freq(chip, res);
109 static void lola_update_rirb(struct lola *chip)
114 wp = lola_readw(chip, BAR0, RIRBWP);
115 if (wp == chip->rirb.wp)
117 chip->rirb.wp = wp;
119 while (chip->rirb.rp != wp) {
120 chip->rirb.rp++;
121 chip->rirb.rp %= LOLA_CORB_ENTRIES;
123 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
124 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
125 res = le32_to_cpu(chip->rirb.buf[rp]);
127 lola_queue_unsol_event(chip, res, res_ex);
128 else if (chip->rirb.cmds) {
129 chip->res = res;
130 chip->res_ex = res_ex;
132 chip->rirb.cmds--;
137 static int rirb_get_response(struct lola *chip, unsigned int *val,
145 if (chip->polling_mode) {
146 spin_lock_irq(&chip->reg_lock);
147 lola_update_rirb(chip);
148 spin_unlock_irq(&chip->reg_lock);
150 if (!chip->rirb.cmds) {
151 *val = chip->res;
153 *extval = chip->res_ex;
155 chip->res, chip->res_ex);
156 if (chip->res_ex & LOLA_RIRB_EX_ERROR) {
157 dev_warn(chip->card->dev, "RIRB ERROR: "
159 chip->last_cmd_nid,
160 chip->last_verb, chip->last_data,
161 chip->last_extdata);
171 dev_warn(chip->card->dev, "RIRB response error\n");
172 if (!chip->polling_mode) {
173 dev_warn(chip->card->dev, "switching to polling mode\n");
174 chip->polling_mode = 1;
181 int lola_codec_write(struct lola *chip, unsigned int nid, unsigned int verb,
186 return corb_send_verb(chip, nid, verb, data, extdata);
190 int lola_codec_read(struct lola *chip, unsigned int nid, unsigned int verb,
198 err = corb_send_verb(chip, nid, verb, data, extdata);
201 err = rirb_get_response(chip, val, extval);
206 int lola_codec_flush(struct lola *chip)
209 return rirb_get_response(chip, &tmp, NULL);
217 struct lola *chip = dev_id;
223 spin_lock(&chip->reg_lock);
228 status = lola_readl(chip, BAR1, DINTSTS);
232 in_sts = lola_readl(chip, BAR1, DIINTSTS);
233 out_sts = lola_readl(chip, BAR1, DOINTSTS);
236 for (i = 0; in_sts && i < chip->pcm[CAPT].num_streams; i++) {
240 reg = lola_dsd_read(chip, i, STS);
246 lola_dsd_write(chip, i, STS, reg);
250 for (i = 0; out_sts && i < chip->pcm[PLAY].num_streams; i++) {
254 reg = lola_dsd_read(chip, i + MAX_STREAM_IN_COUNT, STS);
259 lola_dsd_write(chip, i + MAX_STREAM_IN_COUNT, STS, reg);
264 rbsts = lola_readb(chip, BAR0, RIRBSTS);
267 lola_writeb(chip, BAR0, RIRBSTS, rbsts);
268 rbsts = lola_readb(chip, BAR0, CORBSTS);
271 lola_writeb(chip, BAR0, CORBSTS, rbsts);
273 lola_update_rirb(chip);
278 lola_writel(chip, BAR1, DINTSTS,
283 spin_unlock(&chip->reg_lock);
285 lola_pcm_update(chip, &chip->pcm[CAPT], notify_ins);
286 lola_pcm_update(chip, &chip->pcm[PLAY], notify_outs);
295 static int reset_controller(struct lola *chip)
297 unsigned int gctl = lola_readl(chip, BAR0, GCTL);
302 lola_writel(chip, BAR1, BOARD_MODE, 0);
306 chip->cold_reset = 1;
307 lola_writel(chip, BAR0, GCTL, LOLA_GCTL_RESET);
311 gctl = lola_readl(chip, BAR0, GCTL);
316 dev_err(chip->card->dev, "cannot reset controller\n");
322 static void lola_irq_enable(struct lola *chip)
327 val = (1 << chip->pcm[PLAY].num_streams) - 1;
328 lola_writel(chip, BAR1, DOINTCTL, val);
329 val = (1 << chip->pcm[CAPT].num_streams) - 1;
330 lola_writel(chip, BAR1, DIINTCTL, val);
335 lola_writel(chip, BAR1, DINTCTL, val);
338 static void lola_irq_disable(struct lola *chip)
340 lola_writel(chip, BAR1, DINTCTL, 0);
341 lola_writel(chip, BAR1, DIINTCTL, 0);
342 lola_writel(chip, BAR1, DOINTCTL, 0);
345 static int setup_corb_rirb(struct lola *chip)
350 chip->rb = snd_devm_alloc_pages(&chip->pci->dev, SNDRV_DMA_TYPE_DEV,
352 if (!chip->rb)
355 chip->corb.addr = chip->rb->addr;
356 chip->corb.buf = (__le32 *)chip->rb->area;
357 chip->rirb.addr = chip->rb->addr + 2048;
358 chip->rirb.buf = (__le32 *)(chip->rb->area + 2048);
361 lola_writeb(chip, BAR0, RIRBCTL, 0);
362 lola_writeb(chip, BAR0, CORBCTL, 0);
366 if (!lola_readb(chip, BAR0, RIRBCTL) &&
367 !lola_readb(chip, BAR0, CORBCTL))
373 lola_writel(chip, BAR0, CORBLBASE, (u32)chip->corb.addr);
374 lola_writel(chip, BAR0, CORBUBASE, upper_32_bits(chip->corb.addr));
376 lola_writeb(chip, BAR0, CORBSIZE, 0x02);
378 lola_writew(chip, BAR0, CORBWP, 0);
380 lola_writew(chip, BAR0, CORBRP, LOLA_RBRWP_CLR);
382 lola_writeb(chip, BAR0, CORBCTL, LOLA_RBCTL_DMA_EN);
384 tmp = lola_readb(chip, BAR0, CORBSTS) & LOLA_CORB_INT_MASK;
386 lola_writeb(chip, BAR0, CORBSTS, tmp);
387 chip->corb.wp = 0;
390 lola_writel(chip, BAR0, RIRBLBASE, (u32)chip->rirb.addr);
391 lola_writel(chip, BAR0, RIRBUBASE, upper_32_bits(chip->rirb.addr));
393 lola_writeb(chip, BAR0, RIRBSIZE, 0x02);
395 lola_writew(chip, BAR0, RIRBWP, LOLA_RBRWP_CLR);
397 lola_writew(chip, BAR0, RINTCNT, 1);
399 lola_writeb(chip, BAR0, RIRBCTL, LOLA_RBCTL_DMA_EN | LOLA_RBCTL_IRQ_EN);
401 tmp = lola_readb(chip, BAR0, RIRBSTS) & LOLA_RIRB_INT_MASK;
403 lola_writeb(chip, BAR0, RIRBSTS, tmp);
404 chip->rirb.rp = chip->rirb.cmds = 0;
409 static void stop_corb_rirb(struct lola *chip)
412 lola_writeb(chip, BAR0, RIRBCTL, 0);
413 lola_writeb(chip, BAR0, CORBCTL, 0);
416 static void lola_reset_setups(struct lola *chip)
419 lola_set_granularity(chip, chip->granularity, true);
421 lola_set_clock_index(chip, chip->clock.cur_index);
423 lola_enable_clock_events(chip);
425 lola_setup_all_analog_gains(chip, CAPT, false); /* input, update */
427 lola_set_src_config(chip, chip->input_src_mask, false);
429 lola_setup_all_analog_gains(chip, PLAY, false); /* output, update */
432 static int lola_parse_tree(struct lola *chip)
437 err = lola_read_param(chip, 0, LOLA_PAR_VENDOR_ID, &val);
439 dev_err(chip->card->dev, "Can't read VENDOR_ID\n");
444 dev_err(chip->card->dev, "Unknown codec vendor 0x%x\n", val);
448 err = lola_read_param(chip, 1, LOLA_PAR_FUNCTION_TYPE, &val);
450 dev_err(chip->card->dev, "Can't read FUNCTION_TYPE\n");
454 dev_err(chip->card->dev, "Unknown function type %d\n", val);
458 err = lola_read_param(chip, 1, LOLA_PAR_SPECIFIC_CAPS, &val);
460 dev_err(chip->card->dev, "Can't read SPECCAPS\n");
463 chip->lola_caps = val;
464 chip->pin[CAPT].num_pins = LOLA_AFG_INPUT_PIN_COUNT(chip->lola_caps);
465 chip->pin[PLAY].num_pins = LOLA_AFG_OUTPUT_PIN_COUNT(chip->lola_caps);
466 dev_dbg(chip->card->dev, "speccaps=0x%x, pins in=%d, out=%d\n",
467 chip->lola_caps,
468 chip->pin[CAPT].num_pins, chip->pin[PLAY].num_pins);
470 if (chip->pin[CAPT].num_pins > MAX_AUDIO_INOUT_COUNT ||
471 chip->pin[PLAY].num_pins > MAX_AUDIO_INOUT_COUNT) {
472 dev_err(chip->card->dev, "Invalid Lola-spec caps 0x%x\n", val);
477 err = lola_init_pcm(chip, CAPT, &nid);
480 err = lola_init_pcm(chip, PLAY, &nid);
484 err = lola_init_pins(chip, CAPT, &nid);
487 err = lola_init_pins(chip, PLAY, &nid);
491 if (LOLA_AFG_CLOCK_WIDGET_PRESENT(chip->lola_caps)) {
492 err = lola_init_clock_widget(chip, nid);
497 if (LOLA_AFG_MIXER_WIDGET_PRESENT(chip->lola_caps)) {
498 err = lola_init_mixer_widget(chip, nid);
505 err = lola_enable_clock_events(chip);
512 if (!chip->cold_reset) {
513 lola_reset_setups(chip);
514 chip->cold_reset = 1;
517 if (chip->granularity != LOLA_GRANULARITY_MIN)
518 lola_set_granularity(chip, chip->granularity, true);
524 static void lola_stop_hw(struct lola *chip)
526 stop_corb_rirb(chip);
527 lola_irq_disable(chip);
532 struct lola *chip = card->private_data;
534 if (chip->initialized)
535 lola_stop_hw(chip);
536 lola_free_mixer(chip);
541 struct lola *chip = card->private_data;
549 spin_lock_init(&chip->reg_lock);
550 mutex_init(&chip->open_mutex);
551 chip->card = card;
552 chip->pci = pci;
553 chip->irq = -1;
556 chip->granularity = granularity[dev];
557 switch (chip->granularity) {
559 chip->sample_rate_max = 48000;
562 chip->sample_rate_max = 96000;
565 chip->sample_rate_max = 192000;
568 dev_warn(chip->card->dev,
570 chip->granularity, LOLA_GRANULARITY_MAX);
571 chip->granularity = LOLA_GRANULARITY_MAX;
572 chip->sample_rate_max = 192000;
575 chip->sample_rate_min = sample_rate_min[dev];
576 if (chip->sample_rate_min > chip->sample_rate_max) {
577 dev_warn(chip->card->dev,
579 chip->sample_rate_min);
580 chip->sample_rate_min = 16000;
587 chip->bar[0].addr = pci_resource_start(pci, 0);
588 chip->bar[0].remap_addr = pcim_iomap_table(pci)[0];
589 chip->bar[1].addr = pci_resource_start(pci, 2);
590 chip->bar[1].remap_addr = pcim_iomap_table(pci)[2];
594 err = reset_controller(chip);
599 KBUILD_MODNAME, chip)) {
600 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
603 chip->irq = pci->irq;
604 card->sync_irq = chip->irq;
606 dever = lola_readl(chip, BAR1, DEVER);
607 chip->pcm[CAPT].num_streams = (dever >> 0) & 0x3ff;
608 chip->pcm[PLAY].num_streams = (dever >> 10) & 0x3ff;
609 chip->version = (dever >> 24) & 0xff;
610 dev_dbg(chip->card->dev, "streams in=%d, out=%d, version=0x%x\n",
611 chip->pcm[CAPT].num_streams, chip->pcm[PLAY].num_streams,
612 chip->version);
615 if (chip->pcm[CAPT].num_streams > MAX_STREAM_IN_COUNT ||
616 chip->pcm[PLAY].num_streams > MAX_STREAM_OUT_COUNT ||
617 (!chip->pcm[CAPT].num_streams &&
618 !chip->pcm[PLAY].num_streams)) {
619 dev_err(chip->card->dev, "invalid DEVER = %x\n", dever);
623 err = setup_corb_rirb(chip);
631 card->shortname, chip->bar[0].addr, chip->irq);
634 lola_irq_enable(chip);
636 chip->initialized = 1;
645 struct lola *chip;
656 sizeof(*chip), &card);
661 chip = card->private_data;
667 err = lola_parse_tree(chip);
671 err = lola_create_pcm(chip);
675 err = lola_create_mixer(chip);
679 lola_proc_debug_new(chip);