Lines Matching defs:clock
191 disconnects clock inputs. You should use this information to determine which
197 /* Map the DSP clock detect bits to the generic driver clock
245 * 48 kHz, internal clock, S/PDIF RCA mode */
260 u32 control_reg, clock, base_rate, frq_reg;
262 /* Only set the clock for internal mode. */
265 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
277 clock = 0;
283 clock = E3G_96KHZ;
286 clock = E3G_88KHZ;
289 clock = E3G_48KHZ;
292 clock = E3G_44KHZ;
295 clock = E3G_32KHZ;
298 clock = E3G_CONTINUOUS_CLOCK;
300 clock |= E3G_DOUBLE_SPEED_MODE;
304 control_reg |= clock;
320 "SetSampleRate: %d clock %x\n", rate, control_reg);
328 /* Set the sample clock source to internal, S/PDIF, ADAT */
329 static int set_input_clock(struct echoaudio *chip, u16 clock)
334 /* Mask off the clock select bits */
339 switch (clock) {
367 "Input clock 0x%x not supported for Echo3G\n", clock);
371 chip->input_clock = clock;
382 /* Set clock to "internal" if it's not compatible with the new mode */