Lines Matching refs:chip
58 static void amp_voyetra(struct snd_cs46xx *chip, int change);
74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
86 chip->active_ctrl(chip, 1);
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
156 dev_err(chip->card->dev,
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
176 dev_err(chip->card->dev,
188 dev_dbg(chip->card->dev,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
197 chip->active_ctrl(chip, -1);
204 struct snd_cs46xx *chip = ac97->private_data;
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
229 chip->active_ctrl(chip, 1);
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
278 dev_err(chip->card->dev,
282 chip->active_ctrl(chip, -1);
289 struct snd_cs46xx *chip = ac97->private_data;
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
304 int snd_cs46xx_download(struct snd_cs46xx *chip,
315 dst = chip->region.idx[bank+1].remap_addr + offset;
382 static int load_firmware(struct snd_cs46xx *chip,
394 err = request_firmware(&fw, fw_path, &chip->pci->dev);
468 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
478 dst = chip->region.idx[bank+1].remap_addr + offset;
501 static int load_firmware(struct snd_cs46xx *chip)
506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
509 if (fw->size != sizeof(*chip->ba1)) {
514 chip->ba1 = vmalloc(sizeof(*chip->ba1));
515 if (!chip->ba1) {
520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
525 size += chip->ba1->memory[i].size;
534 static __maybe_unused int snd_cs46xx_download_image(struct snd_cs46xx *chip)
538 struct ba1_struct *ba1 = chip->ba1;
541 err = snd_cs46xx_download(chip,
557 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
578 snd_cs46xx_poke(chip, BA1_DREG, 0);
583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
586 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
602 dev_err(chip->card->dev,
610 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
639 if (cs46xx_wait_for_fifo(chip,1)) {
640 dev_dbg(chip->card->dev,
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
666 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
693 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
699 snd_cs46xx_poke(chip, BA1_SPCR, 0);
708 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
747 spin_lock_irqsave(&chip->reg_lock, flags);
748 snd_cs46xx_poke(chip, BA1_PSRC,
750 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
754 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
821 spin_lock_irqsave(&chip->reg_lock, flags);
822 snd_cs46xx_poke(chip, BA1_CSRC,
824 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
825 snd_cs46xx_poke(chip, BA1_CD,
827 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
851 spin_lock_irqsave(&chip->reg_lock, flags);
852 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
853 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
854 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
855 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
856 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
857 spin_unlock_irqrestore(&chip->reg_lock, flags);
883 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
886 chip->capt.hw_buf.area + rec->hw_data, bytes);
891 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
892 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
906 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
908 ptr = snd_cs46xx_peek(chip, BA1_PBA);
916 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
923 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
925 ptr = snd_cs46xx_peek(chip, BA1_PBA);
933 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
934 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
935 return ptr >> chip->capt.shift;
940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
942 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
963 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
967 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
972 spin_lock(&chip->reg_lock);
976 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
978 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
980 spin_unlock(&chip->reg_lock);
987 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
991 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
993 spin_lock(&chip->reg_lock);
995 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
997 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
999 spin_unlock(&chip->reg_lock);
1013 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1017 spin_lock(&chip->reg_lock);
1021 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1023 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1027 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1029 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1035 spin_unlock(&chip->reg_lock);
1041 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1047 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1050 dev_err(chip->card->dev,
1059 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1061 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm,
1065 dev_err(chip->card->dev,
1070 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1086 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1096 mutex_lock(&chip->spos_mutex);
1098 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1099 mutex_unlock(&chip->spos_mutex);
1105 mutex_unlock(&chip->spos_mutex);
1110 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1111 mutex_unlock(&chip->spos_mutex);
1115 dev_dbg(chip->card->dev,
1149 mutex_unlock(&chip->spos_mutex);
1173 mutex_unlock(&chip->spos_mutex);
1181 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1203 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1213 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1217 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1249 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1253 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1256 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1258 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1259 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1262 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1263 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1264 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1273 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1278 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1281 if (runtime->dma_area != chip->capt.hw_buf.area)
1283 snd_pcm_set_runtime_buffer(substream, &chip->capt.hw_buf);
1286 if (runtime->dma_area == chip->capt.hw_buf.area)
1299 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1302 if (runtime->dma_area != chip->capt.hw_buf.area)
1311 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1314 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1315 chip->capt.shift = 2;
1316 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1317 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1318 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1319 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1326 struct snd_cs46xx *chip = dev_id;
1329 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1338 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1340 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1345 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1351 if (chip->capt.substream)
1352 snd_pcm_period_elapsed(chip->capt.substream);
1376 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1377 if (chip->playback_pcm->substream)
1378 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1380 if ((status1 & HISR_VC1) && chip->pcm) {
1381 if (chip->capt.substream)
1382 snd_pcm_period_elapsed(chip->capt.substream);
1386 if ((status1 & HISR_MIDI) && chip->rmidi) {
1389 spin_lock(&chip->reg_lock);
1390 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1391 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1392 if ((chip->midcr & MIDCR_RIE) == 0)
1394 snd_rawmidi_receive(chip->midi_input, &c, 1);
1396 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1397 if ((chip->midcr & MIDCR_TIE) == 0)
1399 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1400 chip->midcr &= ~MIDCR_TIE;
1401 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1404 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1406 spin_unlock(&chip->reg_lock);
1411 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1479 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1486 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1498 mutex_lock(&chip->spos_mutex);
1507 mutex_unlock(&chip->spos_mutex);
1509 chip->playback_pcm = cpcm; /* HACK */
1512 if (chip->accept_valid)
1514 chip->active_ctrl(chip, 1);
1540 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1542 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1544 mutex_lock(&chip->spos_mutex);
1545 cs46xx_iec958_pre_open (chip);
1546 mutex_unlock(&chip->spos_mutex);
1556 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1558 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1562 mutex_lock(&chip->spos_mutex);
1563 cs46xx_iec958_post_close (chip);
1564 mutex_unlock(&chip->spos_mutex);
1572 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1574 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1575 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1577 chip->capt.substream = substream;
1580 if (chip->accept_valid)
1583 chip->active_ctrl(chip, 1);
1595 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1605 mutex_lock(&chip->spos_mutex);
1607 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1610 mutex_unlock(&chip->spos_mutex);
1612 chip->playback_pcm = NULL;
1617 chip->active_ctrl(chip, -1);
1624 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1626 chip->capt.substream = NULL;
1627 snd_dma_free_pages(&chip->capt.hw_buf);
1628 chip->active_ctrl(chip, -1);
1747 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1752 err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm);
1756 pcm->private_data = chip;
1764 chip->pcm = pcm;
1767 &chip->pci->dev,
1775 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1780 err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1784 pcm->private_data = chip;
1791 chip->pcm_rear = pcm;
1794 &chip->pci->dev,
1800 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1805 err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1809 pcm->private_data = chip;
1816 chip->pcm_center_lfe = pcm;
1819 &chip->pci->dev,
1825 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1830 err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm);
1834 pcm->private_data = chip;
1841 chip->pcm_iec958 = pcm;
1844 &chip->pci->dev,
1856 struct snd_cs46xx *chip = ac97->private_data;
1858 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1859 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1862 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1863 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1864 chip->eapd_switch = NULL;
1867 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1882 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1884 unsigned int val = snd_cs46xx_peek(chip, reg);
1892 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1896 unsigned int old = snd_cs46xx_peek(chip, reg);
1900 snd_cs46xx_poke(chip, reg, val);
1910 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1912 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1913 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1920 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1923 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1924 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1925 cs46xx_dsp_set_dac_volume(chip,
1937 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1939 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1940 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1946 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1949 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1950 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1951 cs46xx_dsp_set_iec958_volume (chip,
1966 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1970 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1972 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1980 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1985 mutex_lock(&chip->spos_mutex);
1986 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1988 cs46xx_dsp_enable_spdif_out(chip);
1990 cs46xx_dsp_disable_spdif_out(chip);
1992 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1993 mutex_unlock(&chip->spos_mutex);
1996 change = chip->dsp_spos_instance->spdif_status_in;
1998 cs46xx_dsp_enable_spdif_in(chip);
2002 cs46xx_dsp_disable_spdif_in(chip);
2004 res = (change != chip->dsp_spos_instance->spdif_status_in);
2017 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2018 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2031 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2032 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2036 cs46xx_dsp_enable_adc_capture(chip);
2039 cs46xx_dsp_disable_adc_capture(chip);
2048 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2049 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2063 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2064 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2068 cs46xx_dsp_enable_pcm_capture(chip);
2071 cs46xx_dsp_disable_pcm_capture(chip);
2081 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2083 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2099 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2100 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2101 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2105 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2107 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2111 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2112 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2117 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2131 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2132 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2134 mutex_lock(&chip->spos_mutex);
2139 mutex_unlock(&chip->spos_mutex);
2147 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2148 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2152 mutex_lock(&chip->spos_mutex);
2164 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2166 mutex_unlock(&chip->spos_mutex);
2184 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2185 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2187 mutex_lock(&chip->spos_mutex);
2192 mutex_unlock(&chip->spos_mutex);
2200 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2201 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2205 mutex_lock(&chip->spos_mutex);
2217 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2219 mutex_unlock(&chip->spos_mutex);
2326 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2328 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2336 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2337 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2415 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2421 ac97.private_data = chip;
2424 if (chip->amplifier_ctrl == amp_voyetra)
2428 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2430 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2431 dev_dbg(chip->card->dev,
2437 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2439 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2440 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2445 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2449 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2451 struct snd_card *card = chip->card;
2463 chip->nr_ac97_codecs = 0;
2464 dev_dbg(chip->card->dev, "detecting primary codec\n");
2465 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
2469 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2471 chip->nr_ac97_codecs = 1;
2474 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2476 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2477 chip->nr_ac97_codecs = 2;
2483 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2492 chip->eapd_switch = snd_ctl_find_id_mixer(chip->card,
2496 if (chip->nr_ac97_codecs == 1) {
2497 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2499 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2502 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2507 if (chip->mixer_init) {
2508 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2509 chip->mixer_init(chip);
2514 chip->amplifier_ctrl(chip, 1);
2523 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2525 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2527 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2532 struct snd_cs46xx *chip = substream->rmidi->private_data;
2534 chip->active_ctrl(chip, 1);
2535 spin_lock_irq(&chip->reg_lock);
2536 chip->uartm |= CS46XX_MODE_INPUT;
2537 chip->midcr |= MIDCR_RXE;
2538 chip->midi_input = substream;
2539 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2540 snd_cs46xx_midi_reset(chip);
2542 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2544 spin_unlock_irq(&chip->reg_lock);
2550 struct snd_cs46xx *chip = substream->rmidi->private_data;
2552 spin_lock_irq(&chip->reg_lock);
2553 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2554 chip->midi_input = NULL;
2555 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2556 snd_cs46xx_midi_reset(chip);
2558 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2560 chip->uartm &= ~CS46XX_MODE_INPUT;
2561 spin_unlock_irq(&chip->reg_lock);
2562 chip->active_ctrl(chip, -1);
2568 struct snd_cs46xx *chip = substream->rmidi->private_data;
2570 chip->active_ctrl(chip, 1);
2572 spin_lock_irq(&chip->reg_lock);
2573 chip->uartm |= CS46XX_MODE_OUTPUT;
2574 chip->midcr |= MIDCR_TXE;
2575 chip->midi_output = substream;
2576 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2577 snd_cs46xx_midi_reset(chip);
2579 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2581 spin_unlock_irq(&chip->reg_lock);
2587 struct snd_cs46xx *chip = substream->rmidi->private_data;
2589 spin_lock_irq(&chip->reg_lock);
2590 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2591 chip->midi_output = NULL;
2592 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2593 snd_cs46xx_midi_reset(chip);
2595 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2597 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2598 spin_unlock_irq(&chip->reg_lock);
2599 chip->active_ctrl(chip, -1);
2606 struct snd_cs46xx *chip = substream->rmidi->private_data;
2608 spin_lock_irqsave(&chip->reg_lock, flags);
2610 if ((chip->midcr & MIDCR_RIE) == 0) {
2611 chip->midcr |= MIDCR_RIE;
2612 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2615 if (chip->midcr & MIDCR_RIE) {
2616 chip->midcr &= ~MIDCR_RIE;
2617 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2620 spin_unlock_irqrestore(&chip->reg_lock, flags);
2626 struct snd_cs46xx *chip = substream->rmidi->private_data;
2629 spin_lock_irqsave(&chip->reg_lock, flags);
2631 if ((chip->midcr & MIDCR_TIE) == 0) {
2632 chip->midcr |= MIDCR_TIE;
2634 while ((chip->midcr & MIDCR_TIE) &&
2635 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2637 chip->midcr &= ~MIDCR_TIE;
2639 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2642 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2645 if (chip->midcr & MIDCR_TIE) {
2646 chip->midcr &= ~MIDCR_TIE;
2647 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2650 spin_unlock_irqrestore(&chip->reg_lock, flags);
2667 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2672 err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi);
2679 rmidi->private_data = chip;
2680 chip->rmidi = rmidi;
2693 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2695 if (snd_BUG_ON(!chip))
2697 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2702 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2704 if (snd_BUG_ON(!chip))
2706 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2711 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2714 if (snd_BUG_ON(!chip))
2717 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2718 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2719 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2746 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2750 chip->gameport = gp = gameport_allocate_port();
2752 dev_err(chip->card->dev,
2758 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2759 gameport_set_dev_parent(gp, &chip->pci->dev);
2760 gameport_set_port_data(gp, chip);
2767 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2768 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2775 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2777 if (chip->gameport) {
2778 gameport_unregister_port(chip->gameport);
2779 chip->gameport = NULL;
2783 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2784 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2808 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2814 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2817 entry->private_data = chip;
2824 cs46xx_dsp_proc_init(card, chip);
2829 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2832 cs46xx_dsp_proc_done(chip);
2837 #define snd_cs46xx_proc_init(card, chip)
2838 #define snd_cs46xx_proc_done(chip)
2844 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2848 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2851 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2853 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2856 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2861 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2862 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2867 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2868 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2873 snd_cs46xx_reset(chip);
2875 snd_cs46xx_proc_stop(chip);
2880 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2886 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2887 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2893 struct snd_cs46xx *chip = card->private_data;
2898 if (chip->active_ctrl)
2899 chip->active_ctrl(chip, 1);
2901 snd_cs46xx_remove_gameport(chip);
2903 if (chip->amplifier_ctrl)
2904 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2906 snd_cs46xx_proc_done(chip);
2908 snd_cs46xx_hw_stop(chip);
2910 if (chip->active_ctrl)
2911 chip->active_ctrl(chip, -chip->amplifier);
2914 if (chip->dsp_spos_instance) {
2915 cs46xx_dsp_spos_destroy(chip);
2916 chip->dsp_spos_instance = NULL;
2919 free_module_desc(chip->modules[idx]);
2921 vfree(chip->ba1);
2926 * initialize chip
2928 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2937 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2938 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2945 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2947 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2949 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2958 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2960 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2963 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2965 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2973 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2975 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2989 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2996 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2997 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2998 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3003 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3013 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3018 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3023 snd_cs46xx_clear_serial_FIFOs(chip);
3028 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3034 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3035 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3036 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3040 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3041 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3042 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3043 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3044 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3059 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3065 dev_err(chip->card->dev,
3067 dev_err(chip->card->dev,
3078 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3085 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3086 dev_dbg(chip->card->dev,
3095 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3097 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3111 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3117 dev_err(chip->card->dev,
3125 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3126 dev_err(chip->card->dev,
3128 dev_err(chip->card->dev,
3130 dev_err(chip->card->dev,
3142 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3149 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3155 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3156 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3165 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3169 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3171 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3173 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3175 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3178 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3181 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3192 snd_cs46xx_reset(chip);
3198 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3200 dev_err(chip->card->dev, "firmware load error [%s]\n",
3204 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3206 dev_err(chip->card->dev, "image download error [%s]\n",
3212 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3215 err = load_firmware(chip);
3220 err = snd_cs46xx_download_image(chip);
3222 dev_err(chip->card->dev, "image download error\n");
3229 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3230 chip->play_ctl = tmp & 0xffff0000;
3231 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3237 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3238 chip->capt.ctl = tmp & 0x0000ffff;
3239 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3243 snd_cs46xx_set_play_sample_rate(chip, 8000);
3244 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3246 snd_cs46xx_proc_start(chip);
3248 cs46xx_enable_stream_irqs(chip);
3252 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3253 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3264 static void amp_none(struct snd_cs46xx *chip, int change)
3269 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3275 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3281 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3284 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3289 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3292 if(chip->nr_ac97_codecs != 2) {
3293 dev_err(chip->card->dev,
3298 modem_power = snd_cs46xx_codec_read (chip,
3303 snd_cs46xx_codec_write(chip,
3310 pin_config = snd_cs46xx_codec_read (chip,
3315 snd_cs46xx_codec_write(chip,
3323 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3327 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3330 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3332 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3334 if ( cs46xx_wait_for_fifo(chip,1) ) {
3335 dev_dbg(chip->card->dev, "FIFO is busy\n");
3350 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3355 if ( cs46xx_wait_for_fifo(chip,200) ) {
3356 dev_dbg(chip->card->dev,
3366 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3371 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3375 cs46xx_wait_for_fifo(chip,200);
3382 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3392 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3398 int old = chip->amplifier;
3402 chip->amplifier += change;
3403 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3406 if (chip->amplifier) {
3414 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3416 if (chip->eapd_switch)
3417 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3418 &chip->eapd_switch->id);
3422 if (chip->amplifier && !old) {
3423 voyetra_setup_eapd_slot(chip);
3428 static void hercules_init(struct snd_cs46xx *chip)
3431 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3432 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3439 static void amp_hercules(struct snd_cs46xx *chip, int change)
3441 int old = chip->amplifier;
3442 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3443 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3445 chip->amplifier += change;
3446 if (chip->amplifier && !old) {
3447 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3449 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3451 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3453 } else if (old && !chip->amplifier) {
3454 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3455 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3456 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3460 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3462 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3465 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3466 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3469 static void hercules_mixer_init (struct snd_cs46xx *chip)
3474 struct snd_card *card = chip->card;
3478 hercules_init(chip);
3480 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3483 if (chip->in_suspend)
3489 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3507 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3509 chip->amplifier += change;
3511 if (chip->amplifier) {
3513 snd_cs46xx_codec_write(chip, 0x4C,
3514 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3515 snd_cs46xx_codec_write(chip, 0x4E,
3516 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3518 snd_cs46xx_codec_write(chip, 0x54,
3519 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3521 snd_cs46xx_codec_write(chip, 0x54,
3522 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3530 * whenever we need to beat on the chip.
3537 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3541 if (!chip->acpi_port)
3544 chip->amplifier += change;
3547 nval = control = inw(chip->acpi_port + 0x10);
3550 if (! chip->amplifier)
3555 outw(nval, chip->acpi_port + 0x10);
3562 static void clkrun_init(struct snd_cs46xx *chip)
3567 chip->acpi_port = 0;
3576 chip->acpi_port = pp << 8;
3721 struct snd_cs46xx *chip = card->private_data;
3725 chip->in_suspend = 1;
3726 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3727 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3729 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3730 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3734 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3736 amp_saved = chip->amplifier;
3738 chip->amplifier_ctrl(chip, -chip->amplifier);
3739 snd_cs46xx_hw_stop(chip);
3741 chip->active_ctrl(chip, -chip->amplifier);
3742 chip->amplifier = amp_saved; /* restore the status */
3749 struct snd_cs46xx *chip = card->private_data;
3756 amp_saved = chip->amplifier;
3757 chip->amplifier = 0;
3758 chip->active_ctrl(chip, 1); /* force to on */
3760 snd_cs46xx_chip_init(chip);
3762 snd_cs46xx_reset(chip);
3764 cs46xx_dsp_resume(chip);
3767 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3769 snd_cs46xx_download_image(chip);
3773 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3774 chip->ac97_general_purpose);
3775 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3776 chip->ac97_powerdown);
3778 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3779 chip->ac97_powerdown);
3783 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3784 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3789 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3790 chip->capt.ctl = tmp & 0x0000ffff;
3791 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3796 snd_cs46xx_set_play_sample_rate(chip, 8000);
3797 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3798 snd_cs46xx_proc_start(chip);
3800 cs46xx_enable_stream_irqs(chip);
3803 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3805 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3806 chip->amplifier = amp_saved;
3807 chip->in_suspend = 0;
3823 struct snd_cs46xx *chip = card->private_data;
3834 spin_lock_init(&chip->reg_lock);
3836 mutex_init(&chip->spos_mutex);
3838 chip->card = card;
3839 chip->pci = pci;
3840 chip->irq = -1;
3845 chip->ba0_addr = pci_resource_start(pci, 0);
3846 chip->ba1_addr = pci_resource_start(pci, 1);
3847 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3848 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3849 dev_err(chip->card->dev,
3851 chip->ba0_addr, chip->ba1_addr);
3855 region = &chip->region.name.ba0;
3857 region->base = chip->ba0_addr;
3860 region = &chip->region.name.data0;
3862 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3865 region = &chip->region.name.data1;
3867 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3870 region = &chip->region.name.pmem;
3872 region->base = chip->ba1_addr + BA1_SP_PMEM;
3875 region = &chip->region.name.reg;
3877 region->base = chip->ba1_addr + BA1_SP_REG;
3886 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3889 chip->amplifier_ctrl = cp->amp;
3890 chip->active_ctrl = cp->active;
3891 chip->mixer_init = cp->mixer_init;
3894 cp->init(chip);
3900 dev_info(chip->card->dev,
3902 chip->amplifier_ctrl = amp_voyetra;
3906 dev_info(chip->card->dev,
3908 chip->active_ctrl = clkrun_hack;
3909 clkrun_init(chip);
3912 if (chip->amplifier_ctrl == NULL)
3913 chip->amplifier_ctrl = amp_none;
3914 if (chip->active_ctrl == NULL)
3915 chip->active_ctrl = amp_none;
3917 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3922 region = &chip->region.idx[idx];
3926 dev_err(chip->card->dev,
3933 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3934 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3937 chip->irq = pci->irq;
3938 card->sync_irq = chip->irq;
3942 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3943 if (!chip->dsp_spos_instance)
3947 err = snd_cs46xx_chip_init(chip);
3951 snd_cs46xx_proc_init(card, chip);
3954 chip->saved_regs = devm_kmalloc_array(&pci->dev,
3956 sizeof(*chip->saved_regs),
3958 if (!chip->saved_regs)
3962 chip->active_ctrl(chip, -1); /* disable CLKRUN */