Lines Matching refs:chip
60 #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
61 #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
498 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
501 writel(val, chip->ba0 + offset);
504 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
506 return readl(chip->ba0 + offset);
519 struct cs4281 *chip = ac97->private_data;
534 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
535 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
536 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
547 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
551 dev_err(chip->card->dev,
558 struct cs4281 *chip = ac97->private_data;
574 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
589 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
590 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
591 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
608 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
612 dev_err(chip->card->dev,
627 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
632 dev_err(chip->card->dev,
642 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
655 struct cs4281 *chip = snd_pcm_substream_chip(substream);
657 spin_lock(&chip->reg_lock);
669 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
684 spin_unlock(&chip->reg_lock);
687 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
688 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
689 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
690 spin_unlock(&chip->reg_lock);
717 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
743 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
744 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
745 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
746 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
747 (chip->src_right_play_slot << 8) |
748 (chip->src_left_rec_slot << 16) |
749 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
753 if (dma->left_slot == chip->src_left_play_slot) {
755 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
756 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
759 if (dma->left_slot == chip->src_left_rec_slot) {
761 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
762 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
768 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
774 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
777 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
779 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
786 struct cs4281 *chip = snd_pcm_substream_chip(substream);
788 spin_lock_irq(&chip->reg_lock);
789 snd_cs4281_mode(chip, dma, runtime, 0, 1);
790 spin_unlock_irq(&chip->reg_lock);
798 struct cs4281 *chip = snd_pcm_substream_chip(substream);
800 spin_lock_irq(&chip->reg_lock);
801 snd_cs4281_mode(chip, dma, runtime, 1, 1);
802 spin_unlock_irq(&chip->reg_lock);
810 struct cs4281 *chip = snd_pcm_substream_chip(substream);
813 dev_dbg(chip->card->dev,
815 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
819 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
874 struct cs4281 *chip = snd_pcm_substream_chip(substream);
878 dma = &chip->dma[0];
893 struct cs4281 *chip = snd_pcm_substream_chip(substream);
897 dma = &chip->dma[1];
942 static int snd_cs4281_pcm(struct cs4281 *chip, int device)
947 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
954 pcm->private_data = chip;
957 chip->pcm = pcm;
959 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
984 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
989 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
990 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1000 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1006 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1007 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1011 snd_cs4281_pokeBA0(chip, regL, volL);
1016 snd_cs4281_pokeBA0(chip, regR, volR);
1048 struct cs4281 *chip = bus->private_data;
1049 chip->ac97_bus = NULL;
1054 struct cs4281 *chip = ac97->private_data;
1056 chip->ac97_secondary = NULL;
1058 chip->ac97 = NULL;
1061 static int snd_cs4281_mixer(struct cs4281 *chip)
1063 struct snd_card *card = chip->card;
1071 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
1074 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1077 ac97.private_data = chip;
1079 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);
1082 if (chip->dual_codec) {
1084 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary);
1088 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip));
1091 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip));
1105 struct cs4281 *chip = entry->private_data;
1108 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1109 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1117 struct cs4281 *chip = entry->private_data;
1119 if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1129 struct cs4281 *chip = entry->private_data;
1131 if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1144 static void snd_cs4281_proc_init(struct cs4281 *chip)
1148 snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
1149 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1151 entry->private_data = chip;
1155 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1157 entry->private_data = chip;
1171 struct cs4281 *chip = gameport_get_port_data(gameport);
1173 if (snd_BUG_ON(!chip))
1175 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1180 struct cs4281 *chip = gameport_get_port_data(gameport);
1182 if (snd_BUG_ON(!chip))
1184 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1191 struct cs4281 *chip = gameport_get_port_data(gameport);
1194 if (snd_BUG_ON(!chip))
1197 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1198 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1199 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1231 static int snd_cs4281_create_gameport(struct cs4281 *chip)
1235 chip->gameport = gp = gameport_allocate_port();
1237 dev_err(chip->card->dev,
1243 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1244 gameport_set_dev_parent(gp, &chip->pci->dev);
1249 gameport_set_port_data(gp, chip);
1251 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1252 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1259 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1261 if (chip->gameport) {
1262 gameport_unregister_port(chip->gameport);
1263 chip->gameport = NULL;
1267 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1268 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1273 struct cs4281 *chip = card->private_data;
1275 snd_cs4281_free_gameport(chip);
1278 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1280 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1282 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1285 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1291 struct cs4281 *chip = card->private_data;
1297 spin_lock_init(&chip->reg_lock);
1298 chip->card = card;
1299 chip->pci = pci;
1300 chip->irq = -1;
1306 chip->dual_codec = dual_codec;
1311 chip->ba0_addr = pci_resource_start(pci, 0);
1312 chip->ba1_addr = pci_resource_start(pci, 1);
1314 chip->ba0 = pcim_iomap_table(pci)[0];
1315 chip->ba1 = pcim_iomap_table(pci)[1];
1318 IRQF_SHARED, KBUILD_MODNAME, chip)) {
1322 chip->irq = pci->irq;
1323 card->sync_irq = chip->irq;
1326 err = snd_cs4281_chip_init(chip);
1330 snd_cs4281_proc_init(chip);
1334 static int snd_cs4281_chip_init(struct cs4281 *chip)
1340 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1341 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1343 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1346 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1348 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1349 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1351 dev_err(chip->card->dev,
1360 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1362 tmp = snd_cs4281_peekBA0(chip, BA0_SERC1);
1364 dev_err(chip->card->dev,
1368 tmp = snd_cs4281_peekBA0(chip, BA0_SERC2);
1370 dev_err(chip->card->dev,
1376 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1385 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1386 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1390 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1397 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1399 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1402 if (chip->dual_codec)
1403 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1408 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1409 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1415 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1417 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1428 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1433 dev_err(chip->card->dev, "DLLRDY not seen\n");
1443 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1454 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1459 dev_err(chip->card->dev,
1461 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1465 if (chip->dual_codec) {
1468 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1472 dev_info(chip->card->dev,
1474 chip->dual_codec = 0;
1483 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1496 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1503 dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1512 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1518 struct cs4281_dma *dma = &chip->dma[tmp];
1529 snd_cs4281_pokeBA0(chip, dma->regFCR,
1536 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1537 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1538 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1539 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1542 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1545 BA0_FCR_OF(chip->dma[0].fifo_offset);
1546 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1547 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1548 (chip->src_right_play_slot << 8) |
1549 (chip->src_left_rec_slot << 16) |
1550 (chip->src_right_rec_slot << 24));
1553 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1554 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1557 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1559 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1574 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1576 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1578 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1583 struct cs4281 *chip = substream->rmidi->private_data;
1585 spin_lock_irq(&chip->reg_lock);
1586 chip->midcr |= BA0_MIDCR_RXE;
1587 chip->midi_input = substream;
1588 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1589 snd_cs4281_midi_reset(chip);
1591 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1593 spin_unlock_irq(&chip->reg_lock);
1599 struct cs4281 *chip = substream->rmidi->private_data;
1601 spin_lock_irq(&chip->reg_lock);
1602 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1603 chip->midi_input = NULL;
1604 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1605 snd_cs4281_midi_reset(chip);
1607 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1609 chip->uartm &= ~CS4281_MODE_INPUT;
1610 spin_unlock_irq(&chip->reg_lock);
1616 struct cs4281 *chip = substream->rmidi->private_data;
1618 spin_lock_irq(&chip->reg_lock);
1619 chip->uartm |= CS4281_MODE_OUTPUT;
1620 chip->midcr |= BA0_MIDCR_TXE;
1621 chip->midi_output = substream;
1622 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1623 snd_cs4281_midi_reset(chip);
1625 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1627 spin_unlock_irq(&chip->reg_lock);
1633 struct cs4281 *chip = substream->rmidi->private_data;
1635 spin_lock_irq(&chip->reg_lock);
1636 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1637 chip->midi_output = NULL;
1638 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1639 snd_cs4281_midi_reset(chip);
1641 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1643 chip->uartm &= ~CS4281_MODE_OUTPUT;
1644 spin_unlock_irq(&chip->reg_lock);
1651 struct cs4281 *chip = substream->rmidi->private_data;
1653 spin_lock_irqsave(&chip->reg_lock, flags);
1655 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1656 chip->midcr |= BA0_MIDCR_RIE;
1657 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1660 if (chip->midcr & BA0_MIDCR_RIE) {
1661 chip->midcr &= ~BA0_MIDCR_RIE;
1662 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1665 spin_unlock_irqrestore(&chip->reg_lock, flags);
1671 struct cs4281 *chip = substream->rmidi->private_data;
1674 spin_lock_irqsave(&chip->reg_lock, flags);
1676 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1677 chip->midcr |= BA0_MIDCR_TIE;
1679 while ((chip->midcr & BA0_MIDCR_TIE) &&
1680 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1682 chip->midcr &= ~BA0_MIDCR_TIE;
1684 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1687 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1690 if (chip->midcr & BA0_MIDCR_TIE) {
1691 chip->midcr &= ~BA0_MIDCR_TIE;
1692 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1695 spin_unlock_irqrestore(&chip->reg_lock, flags);
1712 static int snd_cs4281_midi(struct cs4281 *chip, int device)
1717 err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi);
1724 rmidi->private_data = chip;
1725 chip->rmidi = rmidi;
1735 struct cs4281 *chip = dev_id;
1739 if (chip == NULL)
1741 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1743 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1750 cdma = &chip->dma[dma];
1751 spin_lock(&chip->reg_lock);
1753 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1759 chip->spurious_dhtc_irq++;
1760 spin_unlock(&chip->reg_lock);
1765 chip->spurious_dtc_irq++;
1766 spin_unlock(&chip->reg_lock);
1769 spin_unlock(&chip->reg_lock);
1774 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1777 spin_lock(&chip->reg_lock);
1778 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1779 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1780 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1782 snd_rawmidi_receive(chip->midi_input, &c, 1);
1784 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1785 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1787 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1788 chip->midcr &= ~BA0_MIDCR_TIE;
1789 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1792 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1794 spin_unlock(&chip->reg_lock);
1798 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1811 struct cs4281 *chip = opl3->private_data;
1815 port = chip->ba0 + BA0_B1AP; /* right port */
1817 port = chip->ba0 + BA0_B0AP; /* left port */
1835 struct cs4281 *chip;
1847 sizeof(*chip), &card);
1850 chip = card->private_data;
1856 err = snd_cs4281_mixer(chip);
1859 err = snd_cs4281_pcm(chip, 0);
1862 err = snd_cs4281_midi(chip, 0);
1868 opl3->private_data = chip;
1874 snd_cs4281_create_gameport(chip);
1879 chip->ba0_addr,
1880 chip->irq);
1923 struct cs4281 *chip = card->private_data;
1928 snd_ac97_suspend(chip->ac97);
1929 snd_ac97_suspend(chip->ac97_secondary);
1931 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1933 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1936 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
1941 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
1944 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1947 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1950 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1953 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1955 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1957 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1964 struct cs4281 *chip = card->private_data;
1968 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1970 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1972 snd_cs4281_chip_init(chip);
1977 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
1979 snd_ac97_resume(chip->ac97);
1980 snd_ac97_resume(chip->ac97_secondary);
1982 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1984 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);