Lines Matching defs:tmp
1336 unsigned int tmp;
1341 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1342 if (tmp & BA0_EPPMC_FPDN)
1343 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1346 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1347 if (tmp != BA0_CFLR_DEFAULT) {
1349 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1350 if (tmp != BA0_CFLR_DEFAULT) {
1352 "CFLR setup failed (0x%x)\n", tmp);
1362 tmp = snd_cs4281_peekBA0(chip, BA0_SERC1);
1363 if (tmp != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1365 "SERC1 AC'97 check failed (0x%x)\n", tmp);
1368 tmp = snd_cs4281_peekBA0(chip, BA0_SERC2);
1369 if (tmp != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1371 "SERC2 AC'97 check failed (0x%x)\n", tmp);
1517 for (tmp = 0; tmp < 4; tmp++) {
1518 struct cs4281_dma *dma = &chip->dma[tmp];
1519 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1520 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1521 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1522 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1523 dma->regDMR = BA0_DMR0 + (tmp * 8);
1524 dma->regDCR = BA0_DCR0 + (tmp * 8);
1525 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1526 dma->regFCR = BA0_FCR0 + (tmp * 4);
1527 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1528 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;