Lines Matching defs:BA0_CLKCR1
205 #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
1280 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1385 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1415 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1417 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1428 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1931 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1933 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1950 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1955 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1957 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1968 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1970 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1982 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1984 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);