Lines Matching refs:cm
497 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
499 outl(data, cm->iobase + cmd);
502 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
504 return inl(cm->iobase + cmd);
508 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
510 outw(data, cm->iobase + cmd);
513 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
515 return inw(cm->iobase + cmd);
519 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
521 outb(data, cm->iobase + cmd);
524 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
526 return inb(cm->iobase + cmd);
530 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
533 val = oval = inl(cm->iobase + cmd);
537 outl(val, cm->iobase + cmd);
541 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
544 val = oval = inl(cm->iobase + cmd);
548 outl(val, cm->iobase + cmd);
553 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
556 val = oval = inb(cm->iobase + cmd);
560 outb(val, cm->iobase + cmd);
564 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
567 val = oval = inb(cm->iobase + cmd);
571 outb(val, cm->iobase + cmd);
646 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
657 snd_cmipci_write_b(cm, reg, rate>>8);
658 snd_cmipci_write_b(cm, reg, rate&0xff);
667 struct cmipci *cm = snd_pcm_substream_chip(substream);
669 mutex_lock(&cm->open_mutex);
670 if (cm->opened[CM_CH_PLAY]) {
671 mutex_unlock(&cm->open_mutex);
675 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
676 mutex_unlock(&cm->open_mutex);
681 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
683 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
684 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
685 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
710 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
713 if (!cm->can_multi_ch || !rec->ch)
719 if (cm->can_multi_ch) {
720 spin_lock_irq(&cm->reg_lock);
722 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
723 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
725 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
726 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
729 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
731 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
733 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
734 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
736 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
737 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
740 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
742 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
743 spin_unlock_irq(&cm->reg_lock);
753 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
769 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
770 dev_dbg(cm->card->dev, "cannot set dac channels\n");
784 spin_lock_irq(&cm->reg_lock);
788 snd_cmipci_write(cm, reg, rec->offset);
791 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
792 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
797 cm->ctrl &= ~val;
799 cm->ctrl |= val;
800 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
801 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
815 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
823 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
824 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
827 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
835 if (cm->can_96k) {
839 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
840 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
842 if (!rec->is_dac && cm->chip_version) {
844 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
846 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
850 spin_unlock_irq(&cm->reg_lock);
858 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
869 spin_lock(&cm->reg_lock);
874 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
875 cm->ctrl |= chen;
877 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
878 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
883 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
885 cm->ctrl &= ~chen;
886 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
887 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
892 cm->ctrl |= pause;
893 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
897 cm->ctrl &= ~pause;
898 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
904 spin_unlock(&cm->reg_lock);
911 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
922 rem = snd_cmipci_read_w(cm, reg);
926 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
932 ptr = snd_cmipci_read(cm, reg) - rec->offset;
947 struct cmipci *cm = snd_pcm_substream_chip(substream);
948 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
953 struct cmipci *cm = snd_pcm_substream_chip(substream);
954 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
966 struct cmipci *cm = snd_pcm_substream_chip(substream);
967 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
972 struct cmipci *cm = snd_pcm_substream_chip(substream);
973 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
1107 static int save_mixer_state(struct cmipci *cm)
1109 if (! cm->mixer_insensitive) {
1117 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1122 cm->mixer_res_status[i] = val->value.integer.value[0];
1125 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1130 snd_ctl_notify(cm->card, event, &ctl->id);
1134 cm->mixer_insensitive = 1;
1141 static void restore_mixer_state(struct cmipci *cm)
1143 if (cm->mixer_insensitive) {
1150 cm->mixer_insensitive = 0; /* at first clear this;
1153 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1161 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1162 val->value.integer.value[0] = cm->mixer_res_status[i];
1166 snd_ctl_notify(cm->card, event, &ctl->id);
1174 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1178 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1180 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1182 if (cm->can_ac3_hw) {
1185 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1186 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1189 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1191 if (cm->chip_version == 33) {
1193 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1195 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1201 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1202 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1204 if (cm->can_ac3_hw) {
1207 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1208 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1210 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1211 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1214 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1215 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1216 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1221 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1228 err = save_mixer_state(cm);
1233 spin_lock_irq(&cm->reg_lock);
1234 cm->spdif_playback_avail = up;
1237 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1238 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1239 if (cm->spdif_playback_enabled)
1240 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1241 setup_ac3(cm, subs, do_ac3, rate);
1244 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1246 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1248 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1250 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1253 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1254 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1255 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1256 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1257 setup_ac3(cm, subs, 0, 0);
1259 spin_unlock_irq(&cm->reg_lock);
1271 struct cmipci *cm = snd_pcm_substream_chip(substream);
1278 if (do_spdif && cm->can_ac3_hw)
1279 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1280 err = setup_spdif_playback(cm, substream, do_spdif, do_ac3);
1283 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1289 struct cmipci *cm = snd_pcm_substream_chip(substream);
1292 if (cm->can_ac3_hw)
1293 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1296 err = setup_spdif_playback(cm, substream, 1, do_ac3);
1299 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1310 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1320 snd_cmipci_write(cm, reg, val);
1324 set_dac_channels(cm, rec, 2);
1325 spin_lock_irq(&cm->reg_lock);
1326 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1329 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1330 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1333 if (cm->can_96k)
1335 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1338 cm->ctrl |= CM_CHEN0 << rec->ch;
1339 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1340 spin_unlock_irq(&cm->reg_lock);
1345 spin_lock_irq(&cm->reg_lock);
1346 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1348 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1349 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1350 spin_unlock_irq(&cm->reg_lock);
1358 struct cmipci *cm = snd_pcm_substream_chip(substream);
1359 setup_spdif_playback(cm, substream, 0, 0);
1360 restore_mixer_state(cm);
1361 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1367 struct cmipci *cm = snd_pcm_substream_chip(substream);
1368 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1375 struct cmipci *cm = snd_pcm_substream_chip(substream);
1376 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1382 struct cmipci *cm = snd_pcm_substream_chip(substream);
1384 spin_lock_irq(&cm->reg_lock);
1385 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1386 if (cm->can_96k) {
1388 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1390 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1393 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1395 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1397 spin_unlock_irq(&cm->reg_lock);
1399 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1404 struct cmipci *cm = snd_pcm_substream_chip(subs);
1406 spin_lock_irq(&cm->reg_lock);
1407 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1408 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1409 spin_unlock_irq(&cm->reg_lock);
1420 struct cmipci *cm = dev_id;
1424 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1429 spin_lock(&cm->reg_lock);
1434 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1435 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1436 spin_unlock(&cm->reg_lock);
1438 if (cm->rmidi && (status & CM_UARTINT))
1439 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1441 if (cm->pcm) {
1442 if ((status & CM_CHINT0) && cm->channel[0].running)
1443 snd_pcm_period_elapsed(cm->channel[0].substream);
1444 if ((status & CM_CHINT1) && cm->channel[1].running)
1445 snd_pcm_period_elapsed(cm->channel[1].substream);
1586 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1595 mutex_lock(&cm->open_mutex);
1596 if (cm->opened[ch]) {
1597 mutex_unlock(&cm->open_mutex);
1600 cm->opened[ch] = mode;
1601 cm->channel[ch].substream = subs;
1604 cm->channel[ch].is_dac = 0;
1605 spin_lock_irq(&cm->reg_lock);
1606 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1607 spin_unlock_irq(&cm->reg_lock);
1609 mutex_unlock(&cm->open_mutex);
1613 static void close_device_check(struct cmipci *cm, int mode)
1617 mutex_lock(&cm->open_mutex);
1618 if (cm->opened[ch] == mode) {
1619 if (cm->channel[ch].substream) {
1620 snd_cmipci_ch_reset(cm, ch);
1621 cm->channel[ch].running = 0;
1622 cm->channel[ch].substream = NULL;
1624 cm->opened[ch] = 0;
1625 if (! cm->channel[ch].is_dac) {
1627 cm->channel[ch].is_dac = 1;
1628 spin_lock_irq(&cm->reg_lock);
1629 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1630 spin_unlock_irq(&cm->reg_lock);
1633 mutex_unlock(&cm->open_mutex);
1641 struct cmipci *cm = snd_pcm_substream_chip(substream);
1645 err = open_device_check(cm, CM_OPEN_PLAYBACK, substream);
1649 if (cm->chip_version == 68) {
1653 } else if (cm->chip_version == 55) {
1662 cm->dig_pcm_status = cm->dig_status;
1668 struct cmipci *cm = snd_pcm_substream_chip(substream);
1672 err = open_device_check(cm, CM_OPEN_CAPTURE, substream);
1676 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1679 } else if (cm->chip_version == 55) {
1693 struct cmipci *cm = snd_pcm_substream_chip(substream);
1698 err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream);
1702 mutex_lock(&cm->open_mutex);
1703 if (! cm->opened[CM_CH_PLAY]) {
1704 if (cm->can_multi_ch) {
1705 runtime->hw.channels_max = cm->max_channels;
1706 if (cm->max_channels == 4)
1708 else if (cm->max_channels == 6)
1710 else if (cm->max_channels == 8)
1714 mutex_unlock(&cm->open_mutex);
1715 if (cm->chip_version == 68) {
1719 } else if (cm->chip_version == 55) {
1733 struct cmipci *cm = snd_pcm_substream_chip(substream);
1738 err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream);
1741 if (cm->can_ac3_hw) {
1743 if (cm->chip_version >= 37) {
1747 if (cm->can_96k) {
1756 cm->dig_pcm_status = cm->dig_status;
1762 struct cmipci *cm = snd_pcm_substream_chip(substream);
1767 err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream);
1771 if (cm->can_96k && !(cm->chip_version == 68)) {
1786 struct cmipci *cm = snd_pcm_substream_chip(substream);
1787 close_device_check(cm, CM_OPEN_PLAYBACK);
1793 struct cmipci *cm = snd_pcm_substream_chip(substream);
1794 close_device_check(cm, CM_OPEN_CAPTURE);
1800 struct cmipci *cm = snd_pcm_substream_chip(substream);
1801 close_device_check(cm, CM_OPEN_PLAYBACK2);
1802 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1808 struct cmipci *cm = snd_pcm_substream_chip(substream);
1809 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1815 struct cmipci *cm = snd_pcm_substream_chip(substream);
1816 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1873 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1878 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1885 pcm->private_data = cm;
1888 cm->pcm = pcm;
1891 &cm->pci->dev, 64*1024, 128*1024);
1896 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1901 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1907 pcm->private_data = cm;
1910 cm->pcm2 = pcm;
1913 &cm->pci->dev, 64*1024, 128*1024);
1918 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1923 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1930 pcm->private_data = cm;
1933 cm->pcm_spdif = pcm;
1936 &cm->pci->dev, 64*1024, 128*1024);
1939 snd_pcm_alt_chmaps, cm->max_channels, 0,
2024 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2029 spin_lock_irq(&cm->reg_lock);
2030 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2035 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2040 spin_unlock_irq(&cm->reg_lock);
2047 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2064 spin_lock_irq(&cm->reg_lock);
2065 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2070 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2071 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2076 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2078 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2079 spin_unlock_irq(&cm->reg_lock);
2106 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2111 spin_lock_irq(&cm->reg_lock);
2112 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2113 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2114 spin_unlock_irq(&cm->reg_lock);
2125 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2131 spin_lock_irq(&cm->reg_lock);
2132 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2133 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2141 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2142 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2143 spin_unlock_irq(&cm->reg_lock);
2196 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2201 spin_lock_irq(&cm->reg_lock);
2202 oreg = inb(cm->iobase + reg.left_reg);
2213 spin_unlock_irq(&cm->reg_lock);
2220 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2225 spin_lock_irq(&cm->reg_lock);
2226 oreg = inb(cm->iobase + reg.left_reg);
2239 outb(nreg, cm->iobase + reg.left_reg);
2240 spin_unlock_irq(&cm->reg_lock);
2250 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2257 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2258 if (cm->mixer_insensitive) {
2325 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2327 spin_lock_irq(&cm->reg_lock);
2328 if (args->ac3_sensitive && cm->mixer_insensitive) {
2330 spin_unlock_irq(&cm->reg_lock);
2334 val = inb(cm->iobase + args->reg);
2336 val = snd_cmipci_read(cm, args->reg);
2338 spin_unlock_irq(&cm->reg_lock);
2358 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2360 spin_lock_irq(&cm->reg_lock);
2361 if (args->ac3_sensitive && cm->mixer_insensitive) {
2363 spin_unlock_irq(&cm->reg_lock);
2367 val = inb(cm->iobase + args->reg);
2369 val = snd_cmipci_read(cm, args->reg);
2379 outb((unsigned char)val, cm->iobase + args->reg);
2381 snd_cmipci_write(cm, args->reg, val);
2383 spin_unlock_irq(&cm->reg_lock);
2488 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2494 cm->chip_version >= 39 ? 3 : 2, texts);
2497 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2500 if (cm->chip_version >= 39) {
2501 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2505 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2514 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2516 spin_lock_irq(&cm->reg_lock);
2517 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2518 spin_unlock_irq(&cm->reg_lock);
2525 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2528 spin_lock_irq(&cm->reg_lock);
2530 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2532 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2534 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2536 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2537 spin_unlock_irq(&cm->reg_lock);
2552 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2554 spin_lock_irq(&cm->reg_lock);
2556 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2557 spin_unlock_irq(&cm->reg_lock);
2564 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2567 spin_lock_irq(&cm->reg_lock);
2569 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2571 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2572 spin_unlock_irq(&cm->reg_lock);
2639 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2647 if (snd_BUG_ON(!cm || !cm->card))
2650 card = cm->card;
2654 spin_lock_irq(&cm->reg_lock);
2655 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2656 spin_unlock_irq(&cm->reg_lock);
2659 if (cm->chip_version == 68) { // 8768 has no PCM volume
2664 err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm));
2672 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2676 if (! cm->can_multi_ch) {
2677 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2681 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2682 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2685 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2689 if (cm->can_ac3_hw) {
2690 kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm);
2695 kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm);
2700 kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm);
2706 if (cm->chip_version <= 37) {
2709 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2715 if (cm->chip_version >= 39) {
2718 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2729 if (cm->chip_version < 39) {
2730 err = snd_ctl_add(cm->card,
2731 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2738 ctl = snd_ctl_find_id_mixer(cm->card, cm_saved_mixer[idx].name);
2740 cm->mixer_res_ctl[idx] = ctl;
2754 struct cmipci *cm = entry->private_data;
2757 snd_iprintf(buffer, "%s\n", cm->card->longname);
2761 v = inb(cm->iobase + i);
2769 static void snd_cmipci_proc_init(struct cmipci *cm)
2771 snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2788 static void query_chip(struct cmipci *cm)
2793 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2796 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2799 cm->chip_version = 33;
2800 if (cm->do_soft_ac3)
2801 cm->can_ac3_sw = 1;
2803 cm->can_ac3_hw = 1;
2806 cm->chip_version = 37;
2807 cm->can_ac3_hw = 1;
2810 cm->chip_version = 39;
2811 cm->can_ac3_hw = 1;
2814 cm->max_channels = 2;
2817 cm->chip_version = 39;
2819 cm->max_channels = 6;
2821 cm->max_channels = 4;
2823 cm->chip_version = 68;
2824 cm->max_channels = 8;
2825 cm->can_96k = 1;
2827 cm->chip_version = 55;
2828 cm->max_channels = 6;
2829 cm->can_96k = 1;
2831 cm->can_ac3_hw = 1;
2832 cm->can_multi_ch = 1;
2837 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2850 r = devm_request_region(&cm->pci->dev, io_port, 1,
2857 r = devm_request_region(&cm->pci->dev, io_port, 1,
2862 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2866 cm->gameport = gp = gameport_allocate_port();
2868 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2872 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2873 gameport_set_dev_parent(gp, &cm->pci->dev);
2876 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2878 gameport_register_port(cm->gameport);
2883 static void snd_cmipci_free_gameport(struct cmipci *cm)
2885 if (cm->gameport) {
2886 gameport_unregister_port(cm->gameport);
2887 cm->gameport = NULL;
2889 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2893 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2894 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2899 struct cmipci *cm = card->private_data;
2901 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2902 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2903 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2904 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2905 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2906 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2907 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2910 snd_cmipci_mixer_write(cm, 0, 0);
2912 snd_cmipci_free_gameport(cm);
2915 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2925 if (cm->chip_version >= 39) {
2927 iosynth = cm->iobase + CM_REG_FM_PCI;
2928 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2935 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2945 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2947 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2949 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2951 dev_err(cm->card->dev,
2959 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2965 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2966 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2973 struct cmipci *cm = card->private_data;
2989 spin_lock_init(&cm->reg_lock);
2990 mutex_init(&cm->open_mutex);
2991 cm->device = pci->device;
2992 cm->card = card;
2993 cm->pci = pci;
2994 cm->irq = -1;
2995 cm->channel[0].ch = 0;
2996 cm->channel[1].ch = 1;
2997 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3002 cm->iobase = pci_resource_start(pci, 0);
3005 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3009 cm->irq = pci->irq;
3010 card->sync_irq = cm->irq;
3013 pci_set_master(cm->pci);
3019 cm->chip_version = 0;
3020 cm->max_channels = 2;
3021 cm->do_soft_ac3 = soft_ac3[dev];
3025 query_chip(cm);
3027 if (cm->can_multi_ch)
3028 sprintf(cm->card->driver + strlen(cm->card->driver),
3029 "-MC%d", cm->max_channels);
3030 else if (cm->can_ac3_sw)
3031 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3033 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3034 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3037 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3039 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3043 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3044 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3045 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3046 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3047 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3048 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3049 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3051 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3052 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3054 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3056 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3058 if (cm->chip_version) {
3059 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3060 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3063 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3070 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3076 if (cm->chip_version < 68) {
3079 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3104 if (cm->chip_version < 68)
3106 " (model %d)", cm->chip_version);
3111 card->shortname, modelstr, cm->iobase, cm->irq);
3113 if (cm->chip_version >= 39) {
3114 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3117 iomidi = cm->iobase + CM_REG_MPU_PCI;
3133 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3135 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3137 dev_err(cm->card->dev,
3140 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3147 if (cm->chip_version < 68) {
3148 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3154 snd_cmipci_mixer_write(cm, 0, 0);
3156 snd_cmipci_proc_init(cm);
3160 err = snd_cmipci_pcm_new(cm, pcm_index);
3164 err = snd_cmipci_pcm2_new(cm, pcm_index);
3168 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3170 err = snd_cmipci_pcm_spdif_new(cm, pcm_index);
3176 err = snd_cmipci_mixer_new(cm, pcm_spdif_index);
3186 -1, &cm->rmidi);
3188 dev_err(cm->card->dev,
3194 snd_cmipci_set_pll(cm, rates[val], val);
3199 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3202 if (snd_cmipci_create_gameport(cm, dev) < 0)
3203 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3289 struct cmipci *cm = card->private_data;
3296 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3298 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3301 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3308 struct cmipci *cm = card->private_data;
3312 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3313 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3314 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3315 snd_cmipci_mixer_write(cm, 0, 0);
3319 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3321 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);