Lines Matching defs:CM_REG_FUNCTRL1
79 #define CM_REG_FUNCTRL1 0x04
643 * at the register CM_REG_FUNCTRL1 (0x04).
815 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
823 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1238 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1240 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1254 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1256 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1326 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1329 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1385 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1407 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
2410 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2411 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2416 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2422 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2435 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2474 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2477 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2876 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2889 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2907 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3049 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3063 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3135 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3140 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3203 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3268 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,