Lines Matching refs:phw
223 struct hpi_hw_obj *phw = pao->priv;
242 if (hpi_check_control_cache(phw->p_cache, phm, phr))
249 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, phr);
442 struct hpi_hw_obj *phw = pao->priv;
443 phw->ado[dsp_index].pa_parent_adapter = pao;
467 struct hpi_hw_obj *phw = pao->priv;
472 phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
473 phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
474 HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
475 phw->dw2040_HPIDSP);
479 phw->ado[dsp_index].prHPI_control =
480 phw->dw2040_HPIDSP + (CONTROL +
483 phw->ado[dsp_index].prHPI_address =
484 phw->dw2040_HPIDSP + (ADDRESS +
486 phw->ado[dsp_index].prHPI_data =
487 phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
489 phw->ado[dsp_index].prHPI_data_auto_inc =
490 phw->dw2040_HPIDSP + (DATA_AUTOINC +
494 phw->ado[dsp_index].prHPI_control,
495 phw->ado[dsp_index].prHPI_address,
496 phw->ado[dsp_index].prHPI_data,
497 phw->ado[dsp_index].prHPI_data_auto_inc);
499 phw->ado[dsp_index].pa_parent_adapter = pao;
502 phw->pCI2040HPI_error_count = 0;
508 phw->num_dsp = 1;
516 phw->message_buffer_address_on_dsp = 0L;
517 phw->response_buffer_address_on_dsp = 0L;
544 if (phw->num_dsp == 2) {
554 memset(&phw->control_cache[0], 0,
559 hpi_read_word(&phw->ado[0],
563 hpi_read_word(&phw->ado[0],
566 phw->p_cache =
569 &phw->control_cache[0]
571 if (phw->p_cache)
578 if (phw->p_cache)
579 phw->p_cache->adap_idx = pao->index;
586 struct hpi_hw_obj *phw = pao->priv;
589 hpi_free_control_cache(phw->p_cache);
592 iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET);
594 kfree(phw);
629 struct hpi_hw_obj *phw = pao->priv;
666 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
673 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
682 iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
686 iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
692 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
694 phw->ado[0].c_dsp_rev = 'B'; /* revB */
695 phw->ado[1].c_dsp_rev = 'B'; /* revB */
699 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
701 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
705 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
710 for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
711 struct dsp_obj *pdo = &phw->ado[dsp_index];
1077 phw->num_dsp = 2;
1210 struct hpi_hw_obj *phw = pao->priv;
1211 struct dsp_obj *pdo = &phw->ado[dsp_index];
1248 struct hpi_hw_obj *phw = pao->priv;
1249 struct dsp_obj *pdo = &phw->ado[dsp_index];
1286 struct hpi_hw_obj *phw = pao->priv;
1287 struct dsp_obj *pdo = &phw->ado[dsp_index];
1303 if (phw->message_buffer_address_on_dsp == 0) {
1309 phw->message_buffer_address_on_dsp = address;
1315 address = phw->message_buffer_address_on_dsp;
1334 if (phw->response_buffer_address_on_dsp == 0) {
1342 phw->response_buffer_address_on_dsp = address;
1347 address = phw->response_buffer_address_on_dsp;
1405 struct hpi_hw_obj *phw = pao->priv;
1406 struct dsp_obj *pdo = &phw->ado[dsp_index];
1478 struct hpi_hw_obj *phw = pao->priv;
1479 struct dsp_obj *pdo = &phw->ado[dsp_index];
1542 struct hpi_hw_obj *phw = pao->priv;
1543 struct dsp_obj *pdo = &phw->ado[dsp_index];
1568 struct hpi_hw_obj *phw = pao->priv;
1571 hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1574 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1575 phw->pCI2040HPI_error_count++;
1588 struct hpi_hw_obj *phw = pao->priv;
1589 struct dsp_obj *pdo = &phw->ado[dsp_index];
1631 struct hpi_hw_obj *phw = pao->priv;
1632 struct dsp_obj *pdo = &phw->ado[dsp_index];
1679 (u32 *)&phw->control_cache[0],
1731 struct hpi_hw_obj *phw = pao->priv;
1732 u16 num_dsp = phw->num_dsp;