Lines Matching refs:bus
15 static void azx_clear_corbrp(struct hdac_bus *bus)
20 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
26 snd_hdac_chip_readw(bus, CORBRP));
28 snd_hdac_chip_writew(bus, CORBRP, 0);
30 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
35 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
36 snd_hdac_chip_readw(bus, CORBRP));
41 * @bus: HD-audio core bus
43 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
45 WARN_ON_ONCE(!bus->rb.area);
47 spin_lock_irq(&bus->reg_lock);
49 bus->corb.addr = bus->rb.addr;
50 bus->corb.buf = (__le32 *)bus->rb.area;
51 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
52 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
55 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
57 snd_hdac_chip_writew(bus, CORBWP, 0);
60 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
61 if (!bus->corbrp_self_clear)
62 azx_clear_corbrp(bus);
65 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
68 bus->rirb.addr = bus->rb.addr + 2048;
69 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
70 bus->rirb.wp = bus->rirb.rp = 0;
71 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
72 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
73 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
76 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
78 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
80 snd_hdac_chip_writew(bus, RINTCNT, 1);
82 if (bus->not_use_interrupts)
83 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN);
85 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
87 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
88 spin_unlock_irq(&bus->reg_lock);
93 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
98 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
103 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
110 * @bus: HD-audio core bus
112 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
114 spin_lock_irq(&bus->reg_lock);
116 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
117 snd_hdac_chip_writeb(bus, CORBCTL, 0);
118 spin_unlock_irq(&bus->reg_lock);
120 hdac_wait_for_cmd_dmas(bus);
122 spin_lock_irq(&bus->reg_lock);
124 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
125 spin_unlock_irq(&bus->reg_lock);
140 * @bus: HD-audio core bus
145 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
150 spin_lock_irq(&bus->reg_lock);
152 bus->last_cmd[azx_command_addr(val)] = val;
155 wp = snd_hdac_chip_readw(bus, CORBWP);
158 spin_unlock_irq(&bus->reg_lock);
164 rp = snd_hdac_chip_readw(bus, CORBRP);
167 spin_unlock_irq(&bus->reg_lock);
171 bus->rirb.cmds[addr]++;
172 bus->corb.buf[wp] = cpu_to_le32(val);
173 snd_hdac_chip_writew(bus, CORBWP, wp);
175 spin_unlock_irq(&bus->reg_lock);
185 * @bus: HD-audio core bus
188 * The caller needs bus->reg_lock spinlock before calling this.
190 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
196 wp = snd_hdac_chip_readw(bus, RIRBWP);
202 if (wp == bus->rirb.wp)
204 bus->rirb.wp = wp;
206 while (bus->rirb.rp != wp) {
207 bus->rirb.rp++;
208 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
210 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
211 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
212 res = le32_to_cpu(bus->rirb.buf[rp]);
215 dev_err(bus->dev,
217 res, res_ex, bus->rirb.rp, wp);
220 snd_hdac_bus_queue_event(bus, res, res_ex);
221 else if (bus->rirb.cmds[addr]) {
222 bus->rirb.res[addr] = res;
223 bus->rirb.cmds[addr]--;
224 if (!bus->rirb.cmds[addr] &&
225 waitqueue_active(&bus->rirb_wq))
226 wake_up(&bus->rirb_wq);
228 dev_err_ratelimited(bus->dev,
230 res, res_ex, bus->last_cmd[addr]);
238 * @bus: HD-audio core bus
244 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
256 spin_lock_irq(&bus->reg_lock);
257 if (!bus->polling_mode)
258 prepare_to_wait(&bus->rirb_wq, &wait,
260 if (bus->polling_mode)
261 snd_hdac_bus_update_rirb(bus);
262 if (!bus->rirb.cmds[addr]) {
264 *res = bus->rirb.res[addr]; /* the last value */
265 if (!bus->polling_mode)
266 finish_wait(&bus->rirb_wq, &wait);
267 spin_unlock_irq(&bus->reg_lock);
270 spin_unlock_irq(&bus->reg_lock);
274 if (!bus->polling_mode) {
276 } else if (bus->needs_damn_long_delay ||
279 dev_dbg_ratelimited(bus->dev,
281 bus->last_cmd[addr]);
291 if (!bus->polling_mode)
292 finish_wait(&bus->rirb_wq, &wait);
301 * @bus: the pointer to bus object
305 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
311 offset = snd_hdac_chip_readw(bus, LLCH);
315 cur_cap = _snd_hdac_chip_readl(bus, offset);
317 dev_dbg(bus->dev, "Capability version: 0x%x\n",
320 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
324 dev_dbg(bus->dev, "Invalid capability reg read\n");
330 dev_dbg(bus->dev, "Found ML capability\n");
331 bus->mlcap = bus->remap_addr + offset;
335 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
336 bus->gtscap = bus->remap_addr + offset;
341 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
342 bus->ppcap = bus->remap_addr + offset;
347 dev_dbg(bus->dev, "Found SPB capability\n");
348 bus->spbcap = bus->remap_addr + offset;
353 dev_dbg(bus->dev, "Found DRSM capability\n");
354 bus->drsmcap = bus->remap_addr + offset;
358 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
366 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
385 * @bus: HD-audio core bus
389 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
394 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
397 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
405 * @bus: HD-audio core bus
409 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
413 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
416 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
422 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
428 if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
429 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
432 snd_hdac_bus_enter_link_reset(bus);
440 snd_hdac_bus_exit_link_reset(bus);
447 if (!snd_hdac_chip_readb(bus, GCTL)) {
448 dev_dbg(bus->dev, "controller not ready!\n");
453 if (!bus->codec_mask) {
454 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
455 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
463 static void azx_int_enable(struct hdac_bus *bus)
466 snd_hdac_chip_updatel(bus, INTCTL,
472 static void azx_int_disable(struct hdac_bus *bus)
477 list_for_each_entry(azx_dev, &bus->stream_list, list)
481 snd_hdac_chip_writel(bus, INTCTL, 0);
485 static void azx_int_clear(struct hdac_bus *bus)
490 list_for_each_entry(azx_dev, &bus->stream_list, list)
494 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
497 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
500 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
505 * @bus: HD-audio core bus
508 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
510 if (bus->chip_init)
514 snd_hdac_bus_reset_link(bus, full_reset);
517 azx_int_clear(bus);
520 snd_hdac_bus_init_cmd_io(bus);
523 azx_int_enable(bus);
526 if (bus->use_posbuf && bus->posbuf.addr) {
527 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
528 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
531 bus->chip_init = true;
539 * @bus: HD-audio core bus
541 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
543 if (!bus->chip_init)
547 azx_int_disable(bus);
548 azx_int_clear(bus);
551 snd_hdac_bus_stop_cmd_io(bus);
554 if (bus->posbuf.addr) {
555 snd_hdac_chip_writel(bus, DPLBASE, 0);
556 snd_hdac_chip_writel(bus, DPUBASE, 0);
559 bus->chip_init = false;
565 * @bus: HD-audio core bus
571 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
579 list_for_each_entry(azx_dev, &bus->stream_list, list) {
588 ack(bus, azx_dev);
597 * @bus: HD-audio core bus
602 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
606 int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
609 list_for_each_entry(s, &bus->stream_list, list) {
611 err = snd_dma_alloc_pages(dma_type, bus->dev,
621 err = snd_dma_alloc_pages(dma_type, bus->dev,
622 num_streams * 8, &bus->posbuf);
625 list_for_each_entry(s, &bus->stream_list, list)
626 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
629 return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
635 * @bus: HD-audio core bus
637 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
641 list_for_each_entry(s, &bus->stream_list, list) {
646 if (bus->rb.area)
647 snd_dma_free_pages(&bus->rb);
648 if (bus->posbuf.area)
649 snd_dma_free_pages(&bus->posbuf);
661 set_bit(codec->addr, &codec->bus->codec_powered);
663 clear_bit(codec->addr, &codec->bus->codec_powered);