Lines Matching defs:ac97_reg_base
34 static void __iomem *ac97_reg_base;
58 reg_addr = ac97_reg_base +
61 reg_addr = ac97_reg_base +
66 writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
71 if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1) <= 0 &&
72 !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE)) {
74 __func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
80 writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
84 wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1);
100 reg_addr = ac97_reg_base +
103 reg_addr = ac97_reg_base +
107 writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
110 if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE, 1) <= 0 &&
111 !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE)) {
113 __func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
127 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
132 writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
133 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
137 writel(GCR_COLD_RST, ac97_reg_base + GCR);
149 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
156 writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
157 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
165 writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR);
175 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
181 writel(0, ac97_reg_base + GCR);
182 writel(GCR_CLKBPB, ac97_reg_base + GCR);
184 writel(0, ac97_reg_base + GCR);
186 writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
187 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
192 writel(readl(ac97_reg_base + GCR) & (~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN)), ac97_reg_base + GCR);
194 writel(GCR_WARM_RST | GCR_COLD_RST, ac97_reg_base + GCR);
220 while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
223 gsr = readl(ac97_reg_base + GSR) | gsr_bits;
257 while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
260 gsr = readl(ac97_reg_base + GSR) | gsr_bits;
275 u32 gcr = readl(ac97_reg_base + GCR);
278 writel(gcr, ac97_reg_base + GCR);
286 status = readl(ac97_reg_base + GSR);
288 writel(status, ac97_reg_base + GSR);
296 writel(MISR_EOC, ac97_reg_base + MISR);
297 writel(PISR_EOC, ac97_reg_base + PISR);
298 writel(MCSR_EOC, ac97_reg_base + MCSR);
310 writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
330 ac97_reg_base = devm_platform_ioremap_resource(dev, 0);
331 if (IS_ERR(ac97_reg_base)) {
333 return PTR_ERR(ac97_reg_base);
415 writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
433 writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
447 if (!ac97_reg_base)
450 return readl(ac97_reg_base + MODR);
456 if (!ac97_reg_base)
459 return readl(ac97_reg_base + MISR);