Lines Matching defs:fifo
41 #define AACI_ALLINTS 0x084 /* all fifo interrupt status */
43 #define AACI_DR1 0x090 /* data read/written fifo 1 */
44 #define AACI_DR2 0x0b0 /* data read/written fifo 2 */
45 #define AACI_DR3 0x0d0 /* data read/written fifo 3 */
46 #define AACI_DR4 0x0f0 /* data read/written fifo 4 */
49 * TX/RX fifo control register (CR). P48
51 #define CR_FEN (1 << 16) /* fifo enable */
74 #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
75 #define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */
80 #define SR_TXFF (1 << 5) /* tx fifo full */
81 #define SR_RXFF (1 << 4) /* rx fifo full */
82 #define SR_TXHE (1 << 3) /* tx fifo half empty */
83 #define SR_RXHF (1 << 2) /* rx fifo half full */
84 #define SR_TXFE (1 << 1) /* tx fifo empty */
85 #define SR_RXFE (1 << 0) /* rx fifo empty */
90 #define ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */
93 #define ISR_RXINTR (1 << 3) /* rx fifo */
94 #define ISR_TXINTR (1 << 2) /* tx fifo intr */
112 #define ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
113 #define ISR_UR (1 << 5) /* tx fifo underrun */
114 #define ISR_OR (1 << 4) /* rx fifo overrun */
123 #define IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
124 #define IE_UR (1 << 5) /* tx fifo underrun */
125 #define IE_OR (1 << 4) /* rx fifo overrun */
201 void __iomem *fifo;