Lines Matching defs:buf_slot
696 static int smc_ib_map_mr_sg(struct smc_buf_desc *buf_slot, u8 link_idx)
702 sg_num = ib_map_mr_sg(buf_slot->mr[link_idx],
703 buf_slot->sgt[link_idx].sgl,
704 buf_slot->sgt[link_idx].orig_nents,
710 /* Allocate a memory region and map the dma mapped SG list of buf_slot */
712 struct smc_buf_desc *buf_slot, u8 link_idx)
714 if (buf_slot->mr[link_idx])
717 buf_slot->mr[link_idx] =
718 ib_alloc_mr(pd, IB_MR_TYPE_MEM_REG, 1 << buf_slot->order);
719 if (IS_ERR(buf_slot->mr[link_idx])) {
722 rc = PTR_ERR(buf_slot->mr[link_idx]);
723 buf_slot->mr[link_idx] = NULL;
727 if (smc_ib_map_mr_sg(buf_slot, link_idx) !=
728 buf_slot->sgt[link_idx].orig_nents)
735 struct smc_buf_desc *buf_slot)
742 for_each_sg(buf_slot->sgt[lnk->link_idx].sgl, sg,
743 buf_slot->sgt[lnk->link_idx].nents, i) {
759 struct smc_buf_desc *buf_slot,
765 if (!(buf_slot->is_dma_need_sync & (1U << lnk->link_idx)))
769 for_each_sg(buf_slot->sgt[lnk->link_idx].sgl, sg,
770 buf_slot->sgt[lnk->link_idx].nents, i) {
782 struct smc_buf_desc *buf_slot,
788 if (!(buf_slot->is_dma_need_sync & (1U << lnk->link_idx)))
792 for_each_sg(buf_slot->sgt[lnk->link_idx].sgl, sg,
793 buf_slot->sgt[lnk->link_idx].nents, i) {
805 struct smc_buf_desc *buf_slot,
811 buf_slot->sgt[lnk->link_idx].sgl,
812 buf_slot->sgt[lnk->link_idx].orig_nents,
821 struct smc_buf_desc *buf_slot,
824 if (!buf_slot->sgt[lnk->link_idx].sgl->dma_address)
828 buf_slot->sgt[lnk->link_idx].sgl,
829 buf_slot->sgt[lnk->link_idx].orig_nents,
831 buf_slot->sgt[lnk->link_idx].sgl->dma_address = 0;